US 10,951,184 B2Granted

Push-pull dynamic amplifier circuits

AssigneeOmni Design Technologies Inc.

InventorsHae-Seung Lee, Denis Daly

Life of this patent

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Abstract

A push-pull dynamic amplifier is operable in reset and amplification phases. The amplifier includes first NMOS and PMOS input transistors that are electrically coupled to a first input terminal and a first output terminal. Second NMOS and PMOS input transistors are electrically coupled to a second input terminal and a second output terminal. First and second reset switches are electrically coupled to the first and second output terminals, respectively. A power supply switch is electrically coupled to the first and the second PMOS transistors, and a ground switch is electrically coupled to the first and the second NMOS transistors. During the reset phase, the reset switches are closed and the power supply switch and the ground switch are opened. During the amplification phase, the reset switches are opened and the power supply switch and the ground switch are closed.

Claims47

Dependent claims

A dynamic amplifier operable in a reset phase and an amplification phase, comprising:

a power supply having a first voltage level;
a reset voltage source having a second voltage level between a ground level and the first voltage level;
a first and a second input terminal;
a first and a second output terminal;
a first NMOS input transistor electrically coupled to the first input terminal and the first output terminal;
a second NMOS input transistor electrically coupled to the second input terminal and the second output terminal;
a first PMOS input transistor electrically coupled to the first input terminal and the first output terminal;
a second PMOS input transistor electrically coupled to the second input terminal and the second output terminal;
a first reset switch electrically coupled to the first output terminal and the reset voltage source;
a second reset switch electrically coupled to the second output terminal and the reset voltage source;
a power supply switch electrically coupled to the first and the second PMOS input transistors and to the power supply;
and
a ground switch electrically coupled to the first and the second NMOS input transistors;
wherein:
during the reset phase:
the first and the second reset switches are closed, and
the power supply switch and the ground switch are opened, and
during the amplification phase:
the first and the second reset switches are opened, and
the power supply switch and the ground switch are closed.

17 more elements

A dynamic amplifier operable in a reset phase and an amplification phase, comprising:

a power supply having a first voltage level;
a reset voltage source having a second voltage level between a ground level and the first voltage level;
a first, a second, a third, and a fourth input terminal;
a first and a second output terminal;
a first input transistor electrically coupled to the first input terminal and the first output terminal;
a second input transistor electrically coupled to the second input terminal and the second output terminal;
a third input transistor electrically coupled to the third input terminal and the first output terminal;
a fourth input transistor electrically coupled to the fourth input terminal and the second output terminal;
a first reset switch electrically coupled to the first output terminal and the reset voltage source;
a second reset switch electrically coupled to the second output terminal and the reset voltage source;
a power supply switch electrically coupled to the third and fourth input transistors and to the power supply;
and
a ground switch electrically coupled to the first and the second input transistors;
wherein:
during the reset phase:
the first and the second reset switches are closed, and
the power supply switch and the ground switch are opened, and
during the amplification phase:
the first and the second reset switches are opened, and
the power supply switch and the ground switch are closed.

17 more elements

A dynamic amplifier operable in a reset phase and an amplification phase, comprising:

a first, a second, a third, and a fourth input terminal;
a first and a second output terminal;
a first input transistor electrically coupled to the first input terminal and the first output terminal;
a second input transistor electrically coupled to the second input terminal and the second output terminal;
a third input transistor electrically coupled to the third input terminal and the first output terminal;
a fourth input transistor electrically coupled to the fourth input terminal and the second output terminal;
a first reset switch electrically coupled to the first output terminal and the first input terminal;
a second reset switch electrically coupled to the second output terminal and the second input terminal;
a power supply switch electrically coupled to the third and fourth input transistors;
and
a ground switch electrically coupled to the first and the second input transistors;
wherein:
during the reset phase:
the first and the second reset switches are closed, and
the power supply switch and the ground switch are opened, and
during the amplification phase:
the first and the second reset switches are opened, and
the power supply switch and the ground switch are closed.

15 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/407,440Filed 9 May 2019
Published: US 2020/0358409 A112 Nov 2020
Granted: 16 Mar 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H03F 3/265
Push-pull amplifiers; Phase-splitters therefor: with field-effect transistors only
H03F 3/45183
Using MOSFET transistors as the active amplifying circuit: long tailed pairs
H03F 3/45071
Differential amplifiers: with semiconductor devices only
H03F 3/45237
Using MOSFET transistors as the active amplifying circuit: complementary long tailed pairs having parallel inputs and being supplied in series