Electronic envelope detection circuit and corresponding demodulator
AssigneeSTMicroelectronics S.r.l.
InventorLionel Vogt
Life of this patent
Estimating the term…
Abstract
An electronic envelope detection circuit includes an input signal detecting circuit having at least one MOS transistor configured to receive a radiofrequency input signal and to deliver an internal signal on the basis of the input signal. The biasing point of the at least one transistor is controlled by the input signal and a control signal. A processing circuit that is coupled to the input signal detecting circuit is configured to deliver a low-frequency output signal on the basis of the internal signal and further deliver the control signal on the basis of the output signal. In operation, the value of the control signal decreases when the average power of the input signal increases, and vice versa.
Claims29
An electronic envelope detection circuit, comprising:
- an input signal detecting circuit comprising a first MOS transistor and a second MOS transistor having gates configured to receive a radiofrequency input signal, wherein drains of the first and second MOS transistors are jointly coupled to output an internal signal in response to said radiofrequency input signal, wherein the first and second MOS transistors have a biasing point, and wherein the biasing point is controlled by the radiofrequency input signal and a control signal;
- a processing circuit having an input configured to receive the internal signal and configured to generate a low-frequency output signal in response to the internal signal, wherein the processing circuit is further configured to generate the control signal in response to the low-frequency output signal;
- wherein a value of the control signal decreases in response to an increase in an average power of the radiofrequency input signal, and vice versa;
- and
- a transformer comprising an input winding configured to receive the radiofrequency input signal, a first output winding coupled to receive the control signal and further coupled to gates of the first and second MOS transistors, and a second output winding coupled to sources of the first and second MOS transistors.
An electronic envelope detection circuit, comprising:
- an input signal detecting circuit comprising a MOS transistor having a gate configured to receive a radiofrequency input signal and a drain coupled to output an internal signal in response to the radiofrequency input signal, wherein the MOS transistor has a biasing point, and wherein the biasing point is controlled by the radiofrequency input signal and a control signal;
- a processing circuit having an input configured to receive the internal signal and configured to generate a low-frequency output signal in response to the internal signal, wherein the processing circuit is further configured to generate the control signal in response to the low-frequency output signal;
- wherein a value of the control signal decreases in response to an increase in an average power of the input signal, and vice versa;
- and
- a transformer comprising an input winding configured to receive the radiofrequency input signal and coupled between a source of the MOS transistor and a reference voltage node, and an output winding coupled between the gate of the MOS transistor and the processing circuit and configured to receive the control signal.
An electronic envelope detection circuit, comprising:
- an input signal detecting circuit comprising a first MOS transistor and a second MOS transistor having gates configured to receive a radiofrequency input signal in differential mode, wherein drains of the first and second MOS transistors are jointly coupled to output an internal signal in response to said radiofrequency input signal, wherein the first and second MOS transistors have a biasing point, wherein the biasing point is controlled by the radiofrequency input signal and a control signal, wherein sources of the first and second MOS transistors are jointly coupled to a reference voltage node, and wherein gates of the first and second MOS transistors are further coupled to receive the control signal;
- and
- a processing circuit having an input configured to receive the internal signal generated by the input signal detecting circuit and configured to generate a low-frequency output signal in response to the internal signal, wherein the processing circuit is further configured to generate the control signal in response to the low-frequency output signal;
- wherein a value of the control signal decreases in response to an increase in an average power of the input signal, and vice versa.
Dependencies are inferred from the claim text.