Voltage-controlled oscillator, PLL circuit, and CDR device

A voltage-controlled oscillator comprising an inductor, a first capacitive circuit, and a second capacitive circuit, and outputting an oscillation signal having a frequency according to an input control voltage value due to a resonance phenomenon of the inductor, the first capacitive circuit, and the second capacitive circuit,

• wherein each of the first capacitive circuit and the second capacitive circuit includes
• a variable capacitive element provided between a node N1 and a node N2 and having a capacitance value according to a voltage value between the nodes N1 and N2;
• a capacitive element provided between the node N2 and a node N3;
• a detection circuit that applies a bias voltage value to the node N2 and detects an amount of leak current flowing through the variable capacitive element;
• and
• a compensation circuit that causes a current for compensating for the leak current to flow through the node N1 on the basis of a detection result of the detection circuit,
• wherein the inductor is provided between the nodes N3 of the first capacitive circuit and the second capacitive circuit, and
• the nodes N1 of the first capacitive circuit and the second capacitive circuit are electrically connected to each other to receive the control voltage value
• wherein the detection circuit includes
• a MOS transistor M11 of which a source is connected to a first potential supply terminal,
• a MOS transistor M21 of which a source is connected to a second potential supply terminal,
• a resistive unit provided between a drain of each of the MOS transistor M11 and the MOS transistor M21 and the node N2,
• a differential amplifier including a first input terminal connected to the drain of each of the MOS transistor M11 and the MOS transistor M21, a second input terminal to which a bias voltage value is input, and an output terminal connected to a gate of each of the MOS transistor M11 and the MOS transistor M21, and
• the compensation circuit includes
• a MOS transistor M12 of which a source is connected to the first potential supply terminal and a gate is connected to the output terminal of the differential amplifier,
• a MOS transistor M13 provided between the second potential supply terminal and a drain of the MOS transistor M12,
• a MOS transistor M14 that is provided between the second potential supply terminal and the node N1, that constitutes a current mirror circuit together with the MOS transistor M13, and through which a current of the same amount as a current flowing through the MOS transistor M13 flows,
• a MOS transistor M22 of which a source is connected to the second potential supply terminal and a gate is connected to the output terminal of the differential amplifier,
• a MOS transistor M23 provided between the first potential supply terminal and a drain of the MOS transistor M22, and
• a MOS transistor M24 that is provided between the first potential supply terminal and the node N1, that constitutes a current mirror circuit together with the MOS transistor M23, and through which a current of the same amount as a current flowing through the MOS transistor M23 flows.

A capacitive circuit comprising:

• a variable capacitive element provided between a node N1 and a node N2 and having a capacitance value according to a voltage value between the nodes N1 and N2;
• a capacitive element provided between the node N2 and a node N3;
• a detection circuit including:
• a MOS transistor M1 of which a source is connected to a first potential supply terminal,
• a resistive unit provided between a drain of the MOS transistor M1 and the node N2, and
• a differential amplifier including a first input terminal connected to the drain of the MOS transistor M1, a second input terminal to which a bias voltage value is input, and an output terminal connected to a gate of the MOS transistor M1;
• and
• a compensation circuit including:
• a MOS transistor M2 of which a source is connected to the first potential supply terminal and a gate is connected to the output terminal of the differential amplifier,
• a MOS transistor M3 provided between a second potential supply terminal and a drain of the MOS transistor M2, and
• a MOS transistor M4 that is provided between the second potential supply terminal and the node N1, that forms a current mirror circuit together with the MOS transistor M3, and through which a current of the same amount as a current flowing through the MOS transistor M3 flows.

A voltage-controlled oscillator including a control voltage input terminal, first and second output terminals, and a power supply potential supply terminal, the voltage-controlled oscillator comprising:

• a first inductor including one terminal connected to the power supply potential supply terminal and the other terminal connected to the first output terminal;
• a second inductor including one terminal connected to the power supply potential supply terminal and the other terminal connected to the second output terminal;
• a first variable capacitor and a first capacitor connected in series between the control voltage input terminal and the other terminal of the first inductor;
• a second variable capacitor and a second capacitor connected in series between the control voltage input terminal and the other terminal of the second inductor;
• a first current detector connected between a node between the first variable capacitor and the first capacitor and a bias input terminal;
• and
• a first feedback compensator connected between an output terminal of the first current detector and the control voltage input terminal, the first feedback compensator providing a current to the control voltage input terminal based on an amount of a leak current of the first variable capacitor detected by the first current detector.

A capacitive circuit comprising:

• a variable capacitive element provided between a node N1 and a node N2 and having a capacitance value according to a voltage value between the nodes N1 and N2;
• a capacitive element provided between the node N2 and a node N3;
• a detection circuit including:
• a MOS transistor M11 of which a source is connected to a first potential supply terminal,
• a MOS transistor M21 of which a source is connected to a second potential supply terminal,
• a resistive unit provided between a drain of each of the MOS transistor M11 and the MOS transistor M21 and the node N2,
• a differential amplifier including a first input terminal connected to the drain of each of the MOS transistor M11 and the MOS transistor M21, a second input terminal to which a bias voltage value is input, and an output terminal connected to a gate of each of the MOS transistor M11 and the MOS transistor M21;
• and
• compensation circuit including:
• the compensation circuit includes
• a MOS transistor M12 of which a source is connected to the first potential supply terminal and a gate is connected to the output terminal of the differential amplifier,
• a MOS transistor M13 provided between the second potential supply terminal and a drain of the MOS transistor M12,
• a MOS transistor M14 that is provided between the second potential supply terminal and the node N1, that constitutes a current mirror circuit together with the MOS transistor M13, and through which a current of the same amount as a current flowing through the MOS transistor M13 flows,
• a MOS transistor M22 of which a source is connected to the second potential supply terminal and a gate is connected to the output terminal of the differential amplifier,
• a MOS transistor M23 provided between the first potential supply terminal and a drain of the MOS transistor M22, and
• a MOS transistor M24 that is provided between the first potential supply terminal and the node N1, that constitutes a current mirror circuit together with the MOS transistor M23, and through which a current of the same amount as a current flowing through the MOS transistor M23 flows.