RRAM with a barrier layer
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsFu-Chen Chang, Kuo-Chi Tu, Wen-Ting Chu, Chu-Jie Huang
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Abstract
Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell comprising a barrier layer to constrain the movement of metal cations during operation of the RRAM cell. In some embodiments, the RRAM cell further comprises a bottom electrode, a top electrode, a switching layer, and an active metal layer. The switching layer, the barrier layer, and the active metal layer are stacked between the bottom and top electrodes, and the barrier layer is between the switching and active metal layers. The barrier layer is conductive and has a lattice constant less than that of the active metal layer.
Claims20
An integrated chip comprising:
- a substrate;
- and
- a resistive random-access memory (RRAM) cell overlying the substrate, wherein the RRAM cell comprises a bottom electrode and a top electrode, and further comprises a switching layer, a barrier layer, and an active metal layer stacked between the bottom and top electrodes, wherein the barrier layer is conductive and between the switching layer and active metal layers, wherein the barrier layer has a lattice constant less than that of the active metal layer, wherein the RRAM cell is configured to repeatedly form and dissolve a conductive filament in the switching layer, wherein the barrier layer is configured to slow a rate at which metal cations from the active metal layer enter the switching layer while forming the conductive filament, wherein the conductive filament is formed from the metal cations, and wherein the metal cations and the active metal layer share a common metal element.
An integrated chip comprising:
- a bottom electrode;
- a dielectric layer overlying the bottom electrode;
- a barrier layer overlying the dielectric layer, wherein the barrier layer comprises tantalum;
- an aluminum filament in the dielectric layer, wherein the aluminum filament extends upward from the bottom electrode to the barrier layer;
- an aluminum layer overlying the barrier layer;
- and
- a top electrode overlying the aluminum layer;
- wherein the bottom and top electrodes, the dielectric layer, the barrier layer, and the aluminum layer define a memory cell.
A memory cell comprising:
- a bottom electrode;
- a switching layer overlying the bottom electrode and comprising a dielectric;
- a barrier layer overlying the switching layer and being conductive;
- an active metal layer overlying the barrier layer and comprising a metal;
- a top electrode overlying the active metal layer;
- and
- a conductive filament in the switching layer and comprising the metal;
- wherein the active metal layer depends upon less energy than the top electrode to oxidize.
Dependencies are inferred from the claim text.