Substrates and transistors with 2D material channels on 3D geometries
AssigneeSynopsys, Inc.
InventorsVictor Moroz, Joanne Huang, Jamil Kawa
Life of this patent
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AssigneeSynopsys, Inc.
InventorsVictor Moroz, Joanne Huang, Jamil Kawa
Estimating the term…
Roughly described, a transistor is formed with a semiconductor 2D material layer wrapped conformally on at least part of a 3D structure. The 3D structure can be for example a ridge made of a dielectric material, or made of dielectric material alternating longitudinally with a semiconductive or conductive material. Alternatively the 3D structure can be tree-shaped. Other shapes are possible as well. Aspects also include methods for making such structures, as well as integrated circuit layouts defining such structures and methods for developing such layouts, a machine readable data storage medium storing design entries which include some which define such structures and layouts, methods for developing such design entries. Aspects further include corrugated wafers which are prepared as an intermediate product for use in fabricating integrated circuits having a semiconductor 2D material layer disposed conformally on a 3D structure.
A wafer comprising:
An article of manufacture comprising:
A method of making an integrated circuit structure having a transistor device, comprising:
An integrated circuit structure having a transistor device, comprising:
Dependencies are inferred from the claim text.