Inner spacers for gate-all-around semiconductor devices
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYu-Yun Peng, Fu-Ting Yen, Ting-Ting Chen, Keng-Chu Lin, Tsu-Hsiu Perng
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Abstract
Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first semiconductor channel member and a second semiconductor channel member over the first semiconductor channel member and a porous dielectric feature that includes silicon and nitrogen. In the semiconductor device, the porous dielectric feature is sandwiched between the first and second semiconductor channel members and a density of the porous dielectric feature is smaller than a density of silicon nitride.
Claims20
A semiconductor device, comprising:
- a first semiconductor channel member and a second semiconductor channel member over the first semiconductor channel member;
- and
- a porous dielectric feature comprising silicon and nitrogen,
- wherein the porous dielectric feature is sandwiched between the first and second semiconductor channel members,
- wherein a density of the porous dielectric feature is smaller than a density of silicon nitride.
A method of fabricating a semiconductor device, comprising:
- providing a fin element that includes a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers;
- forming a dummy gate structure over a channel region of the fin element;
- etching a source/drain region of the fin element to expose sidewalls of the plurality of first semiconductor layers and sidewalls of the plurality of second semiconductor layers;
- selectively and partially recessing exposed sidewalls of the plurality of second semiconductor layers to form a plurality of recesses;
- depositing an inner spacer layer over the plurality of recesses using an organosilane precursor and a nitrogen-containing gas;
- treating the inner spacer layer;
- and
- etching back the inner spacer layer.
A method of fabricating a semiconductor device, comprising:
- providing a fin element that includes a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers;
- forming a dummy gate structure over a channel region of the fin element;
- etching a source/drain region of the fin element to expose sidewalls of the plurality of first semiconductor layers and sidewalls of the plurality of second semiconductor layers,
- selectively and partially recessing exposed sidewalls of the plurality of second semiconductor layers to form a plurality of recesses;
- depositing an inner spacer layer comprising silicon and nitrogen;
- treating the inner spacer layer;
- and
- etching back the inner spacer layer to form a porous silicon nitride layer that is less dense than silicon nitride.
Dependencies are inferred from the claim text.