Fin field effect transistor (FinFET) device structure with isolation layer and method for forming the same

A fin field effect transistor (FinFET) device structure, comprising:

• a fin structure formed over a substrate;
• a gate structure formed over the fin structure, wherein the gate structure comprises a gate dielectric layer and a gate electrode layer, wherein a topmost surface of the gate dielectric layer is higher than a topmost surface of the gate electrode layer;
• an S/D contact structure formed adjacent to the gate structure;
• an S/D conductive plug formed over the S/D contact structure, wherein the S/D conductive plug is electrically connected to the S/D contact structure;
• a first isolation layer formed on a sidewall surface of the S/D conductive plug, wherein the first isolation layer is made of high-k dielectric material;
• a gate contact structure formed over the gate structure, wherein the gate contact structure is electrically connected to the gate structure, and the gate contact structure comprises a second barrier layer, and the second barrier layer is in direct contact with the gate electrode layer;
• and
• a first dielectric layer over the gate structure;
• an etching stop layer over the first dielectric layer;
• a second dielectric layer over the etching stop layer;
• a second isolation layer formed on a sidewall surface of the gate contact structure, wherein the second isolation layer is made of high-k dielectric material,
• wherein a top surface of the etching stop layer is higher than a bottom surface of the second isolation layer and lower than a top surface of the first isolation layer, and
• wherein the second isolation layer is in direct contact with the gate dielectric layer at a location below the top surface of the gate dielectric layer, and continuously extends from the location below the top surface of the gate dielectric layer to a top surface of the second dielectric layer and above the top surface of the gate dielectric layer.

A method for a fin field effect transistor (FinFET) device structure, comprising:

• forming a gate structure over a fin structure, wherein the gate structure comprises a gate dielectric layer;
• forming an S/D contact structure adjacent to the gate structure;
• forming a dielectric layer over the gate structure and the S/D contact structure;
• forming a first recess and a second recess in the dielectric layer, wherein the first recess is above the S/D contact structure, and the second recess is above the gate structure;
• forming a first isolation layer on sidewall surfaces of the first recess;
• forming a second isolation layer on sidewall surfaces of the second recess, wherein the second isolation layer is in direct contact with the gate dielectric layer at a location below the top surface of the gate dielectric layer, and continuously extends from the location below the top surface of the gate dielectric layer to a top surface of the dielectric layer and above the top surface of the gate dielectric layer;
• forming a barrier layer over the first isolation layer and the second isolation layer, wherein the barrier layer is in direct contact with the dielectric layer;
• forming an S/D conductive plug over the first isolation layer, wherein the S/D conductive plug comprises the barrier layer and a first conductive layer, and the barrier layer is between the first isolation layer and the first conductive layer;
• and
• forming a gate contact structure over the second isolation layer, wherein the gate contact structure comprises the barrier layer and a second conductive layer, and the barrier layer is between the second isolation layer and the second conductive layer.