Method of fabricating a semiconductor device including vertical-type field effect transistors
AssigneeSamsung Electronics Co., Ltd.
InventorsYeoncheol Heo, Sharma Deepak, Kwanyoung Chun
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a substrate with an upper surface and a lower surface, and first to third active patterns extending from the upper surface of the substrate. The first to third active patterns are arranged adjacent to each other in a first direction. The second active pattern is disposed between the first and third active patterns. The semiconductor device also includes a first gate electrode surrounding side surfaces of the first and second active patterns, and a second gate electrode surrounding side surfaces of the third active pattern. Each of the first to third active patterns includes a first impurity region, a channel region, and a second impurity region.
Claims18
A method of fabricating a semiconductor device, comprising:
- forming a device isolation layer in an upper portion of a substrate to define base regions;
- doping the base regions with impurities to form first impurity regions;
- forming a semiconductor layer on a substantially entire upper surface of the substrate;
- doping upper portions of the semiconductor layer with impurities to form second impurity regions;
- patterning the semiconductor layer to form first to third active patterns on the base regions, the first to third active patterns including the first impurity regions;
- forming a spacer layer to cover the first impurity regions, before the forming of the first and second sate electrodes:
- forming a first gate electrode to surround side surfaces of the first and second active patterns;
- and forming a second gate electrode to surround side surfaces of the third active pattern, wherein a distance between the first and second active patterns is a first distance, a distance between the second and third active patterns is a second distance, the second distance is greater than the first distance, the patterning of the semiconductor layer is performed to form recesses in the first impurity regions, and the spacer layer is formed to fill the recesses.
A method of fabricating a semiconductor device, comprising:
- forming a device isolation layer in an upper portion of a substrate to define base regions;
- doping the base regions with impurities to form first impurity regions;
- forming a semiconductor layer on a substantially entire upper surface of the substrate;
- doping upper portions of the semiconductor layer with impurities to form second impurity regions;
- patterning the semiconductor layer to form first to third active patterns on the base regions;
- forming a first gate electrode to surround side surfaces of the first and second active patterns;
- and
- forming a second gate electrode to surround side surfaces of the third active pattern, wherein
- the semiconductor layer comprises crystalline regions on the first impurity regions and an amorphous region on the device isolation layer, and
- the patterning of the semiconductor layer comprises removing the amorphous region.
A method of fabricating a semiconductor device, comprising:
- forming a device isolation layer in an upper portion of a substrate to define base regions;
- doping the base regions with impurities to form first impurity regions;
- forming a semiconductor layer on a substantially entire upper surface of the substrate;
- doping upper portions of the semiconductor layer with impurities to form second impurity regions;
- patterning the semiconductor layer to form first to third active patterns on the base regions and recesses in the first impurity regions;
- forming a spacer layer to cover the first impurity regions and to fill the recesses;
- forming a first gate electrode on the spacer layer to surround side surfaces of the first and second active patterns;
- and
- forming a second gate electrode on the spacer layer to surround side surfaces of the third active pattern.
Dependencies are inferred from the claim text.