Vertical gate all-around transistor

A vertical field effect transistor, comprising:

• a silicon substrate having a front surface and a back surface opposite the front surface;
• a first doped region on the substrate spaced from the front surface of the substrate;
• a second doped region in the silicon substrate, the second doped region extending into the substrate from the front surface, an edge of the second doped region being spaced from the back surface of the substrate;
• a nanowire on the substrate extending between the first doped region and the second doped region, the nanowire including a channel located between the first doped region and the second doped region, the channel having a channel axis that is oriented transverse to the front surface of the silicon substrate;
• an insulating layer on the front surface of the substrate, the insulating layer including a first material;
• a gate, including:
• a gate dielectric on the insulating layer and the channel, the gate dielectric including a second material that is different from the first material;
• and
• a metal gate on the gate dielectric, the metal gate spaced apart from the insulating layer and the channel by the gate dielectric, wherein the gate wraps around the channel in the nanowire, the gate being positioned between the first doped region and the front surface of the substrate;
• a first conductive contact coupled to the first doped region, the gate being spaced from the first conductive contact by the first doped region;
• a second conductive contact coupled to the second doped region and extending from the back surface through the silicon substrate into the second doped region;
• and
• a gate contact in direct contact with the metal gate, the gate contact extending from a surface of the gate proximal to the silicon substrate into a trench insulation region in the silicon substrate and through the insulation layer, the trench insulation region laterally enveloped by silicon material of the silicon substrate and including a liner layer of the first material and a second dielectric material surrounded by the liner layer and the insulation layer.

A CMOS device, comprising:

• a substrate including a silicon layer having a front surface and a back surface opposite the front surface, the silicon layer having a first width in a first direction;
• an insulation layer over the front surface of the substrate and having a first dielectric material;
• a first vertical gate-all-around transistor, having:
• a first doped region in the silicon layer;
• a first channel on the front surface of the silicon layer;
• a second doped region on the first channel and spaced from the silicon layer by the first channel;
• a first gate on the silicon layer and around the first channel;
• a first conductive contact coupled to the first gate and extending along a direction transverse to the front surface of the silicon layer, the first gate being between the first conductive contact and the silicon layer;
• and
• a second conductive contact at the back surface of the silicon layer, the second conductive contact coupled to the first doped region, the first doped region having a second width in the first direction, the first width greater than the second width;
• a second vertical gate-all-around transistor, having:
• a third doped region in the silicon layer;
• a second channel on the front surface of the silicon layer;
• a fourth doped region on the second channel and spaced from the silicon layer by the second channel;
• a second gate on the silicon layer and around the second channel, the second gate spaced laterally apart from the first gate along the first direction;
• a third conductive contact coupled to the second gate, the third conductive contact extending from a surface of the second gate proximal to the silicon layer of the substrate into an insulation region in the silicon layer, the insulation region laterally enveloped by silicon material of the silicon layer and including a liner layer of the first dielectric material and a second dielectric material surrounded by the liner layer and the insulation layer;
• and
• a fourth conductive contact at the back surface of the silicon layer, the fourth conductive contact coupled to the third doped region, the third doped region having a third width in the first direction, the first width greater than the third width;
• and
• a low-k encapsulant on a first surface of the first gate and on a second surface of the second gate, the first and second surfaces respectively spaced apart from the silicon layer by the first gate and the second gate, the low-k encapsulant extending directly between and in contact with respective side surfaces of the first gate and the second gate which face each other, the low-k encapsulant filling an entire space between the first gate and the second gate along the first direction, the low-k encapsulant including one or more of the silicon compounds SiOCN and SiBCN,
• wherein the second conductive contact is spaced laterally apart from the fourth conductive contact, and the third conductive contact is disposed between the second conductive contact and the fourth conductive contact.