Self-aligned high voltage transistor

A transistor comprising:

• a channel region;
• a gate region disposed above the channel region;
• a first implant region;
• a second implant region having a same doping type as the first implant region, but a different doping type than the channel region;
• a first spacer disposed adjacent to a first side of the gate region;
• a second spacer disposed adjacent to a second side of the gate region and having a wider width than the first spacer, wherein the second spacer comprises two or more dielectric spacers;
• a drift region having an edge vertically aligned with an edge of the second spacer and disposed between the channel region and the second implant region, wherein the channel region is disposed between the first implant region and the drift region;
• and
• one or more dielectric regions disposed between portions of the drift region.

A method for fabricating a transistor, comprising:

• forming a gate region above a channel region;
• forming a first implant region;
• forming a second implant region having a same doping type as the first implant region, but a different doping type than the channel region;
• forming a first spacer adjacent to a first side of the gate region;
• forming a second spacer adjacent to a second side of the gate region and having a wider width than the first spacer, wherein the second spacer comprises two or more dielectric spacers;
• forming a drift region having an edge vertically aligned with an edge of the second spacer and disposed between the channel region and the second implant region;
• and
• forming one or more third implant regions disposed between portions of the drift region and between the channel region and the second implant region.