IGBT with fully depletable n- and p-channel regions
AssigneeInfineon Technologies Dresden GmbH
InventorsAnton Mauder, Thomas Kuenzig, Franz-Josef Niedernostheide, Christian Philipp Sandow
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AssigneeInfineon Technologies Dresden GmbH
InventorsAnton Mauder, Thomas Kuenzig, Franz-Josef Niedernostheide, Christian Philipp Sandow
Estimating the term…
A power semiconductor device has a semiconductor body coupled to first and second load terminal structures, the semiconductor body configured to conduct a load current during a conducting state of the device and having a drift region. The power semiconductor device includes a plurality of cells, each cell having: a first mesa in a first cell portion, the first mesa including: a first port region, and a first channel region, the first mesa exhibiting a total extension of less than 100 nm in a lateral direction, and a second mesa in a second cell portion including: a second port region, and a second channel region. A trench structure includes a control electrode structure configured to control the load current by inversion or accumulation. A guidance zone of the second conductivity type is below the second channel region and is displaced from the first and the second channel regions.
A power semiconductor device having a semiconductor body coupled to a first load terminal structure and a second load terminal structure, the semiconductor body comprising a drift region of a first conductivity type and being configured to conduct a load current during a conducting state of the power semiconductor device and to block a load current during a blocking state of the power semiconductor device, wherein the power semiconductor device includes a plurality of cells, each cell comprising:
A power semiconductor device having a semiconductor body coupled to a first load terminal structure and a second load terminal structure, the semiconductor body being configured to conduct a load current and comprising a drift region of a first conductivity type, wherein the power semiconductor device includes a plurality of cells, each cell comprising:
A method of processing a power semiconductor device having a semiconductor body coupled to a first load terminal structure and a second load terminal structure, the semiconductor body being configured to conduct a load current and comprising a drift region of a first conductivity type, wherein the power semiconductor device includes a plurality of cells, each cell comprising:
Dependencies are inferred from the claim text.