Method of manufacturing semiconductor device including non-volatile memories and logic devices

A method for manufacturing a semiconductor device including a non-volatile memory disposed in a memory cell area and a field effect transistor disposed in a logic circuit area, the method comprising:

• forming a cell structure for the non-volatile memory in the memory cell area, the cell structure comprising:
• a stacked structure including a first polysilicon layer disposed over a first dielectric layer, a second dielectric layer disposed over the first polysilicon layer, and a second polysilicon layer disposed over the second dielectric layer;
• and
• third polysilicon layers disposed at both sides of the stacked structure;
• forming a dummy gate structure for the field effect transistor in the logic circuit area, the dummy gate structure comprising:
• a gate dielectric layer disposed over the substrate;
• and
• a dummy logic gate made of polysilicon and disposed over the gate dielectric layer;
• at least partially removing the third polysilicon layers, thereby forming an erase gate space and a select gate space in the memory cell area and not removing the second polysilicon layer, and removing the dummy logic gate, thereby forming a logic gate space in the logic circuit area;
• forming a conductive material in the erase gate space, the select gate space and the logic gate space, thereby forming an erase gate electrode, a select gate electrode and a logic gate electrode;
• and
• forming an interlayer dielectric layer over the erase gate electrode, the select gate electrode, a control gate electrode and a logic gate electrode,
• wherein the control gate electrode is made of the second polysilicon layer.

A method for manufacturing a semiconductor device including a non-volatile memory, the method comprising:

• forming a first dielectric layer over a substrate;
• forming a first polysilicon layer over the first dielectric layer;
• forming a second dielectric layer over the first polysilicon layer;
• forming a second polysilicon layer over the second dielectric layer;
• patterning the second polysilicon layer;
• after the second polysilicon layer is patterned, patterning the second dielectric layer and the first polysilicon layer, thereby forming stacked structures including the second polysilicon layer, the second dielectric layer, the first polysilicon layer as a floating gate, and the first dielectric layer;
• forming a third poly silicon layer so that an erase gate is formed between the stacked structure and selection gates are formed at sides of the stacked structure at which the erase gate are not formed;
• performing a planarization operation, comprising a chemical mechanical polishing process, in the stacked structures and the third poly silicon layer such that the second polysilicon layer and the third polysilicon layer are exposed;
• after the planarization operation is performed, removing the third polysilicon layer, thereby forming an erase gate space and a select gate space, and not removing the second polysilicon layer;
• forming a conductive material over a remaining third polysilicon layer in the erase gate space and the select gate space, respectively, thereby forming an erase gate electrode, a select gate electrode and a logic gate electrode;
• and
• forming an interlayer dielectric layer over the erase gate electrode, the select gate electrode, a control gate electrode and a logic gate electrode,
• wherein the control gate electrode is made of the second polysilicon layer.