Dishing prevention dummy structures for semiconductor devices
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Fu-Jier Fan, Kong-Beng Thei, Yi-Sheng Chen, Szu-Hsien Liu
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Abstract
In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.
Claims20
An integrated circuit (IC), comprising:
- an inner isolation structure disposed in a semiconductor substrate, wherein an inner perimeter of the inner isolation structure demarcates a device region;
- an inner ring-shaped well disposed in the semiconductor substrate and laterally surrounding the inner isolation structure;
- an outer isolation structure disposed in the semiconductor substrate and laterally surrounding both the inner ring-shaped well and the inner isolation structure;
- and
- a plurality of dishing prevention dummy gates arranged over both the inner ring-shaped well and the outer isolation structure, wherein a first dishing prevention dummy gate of the plurality of dishing prevention dummy gates comprises a first dummy gate dielectric disposed over the inner isolation structure, and wherein sidewalls of the first dummy gate dielectric are disposed between the inner perimeter of the inner isolation structure and an outer perimeter of the inner isolation structure.
An integrated circuit (IC), comprising:
- an inner isolation structure disposed in a semiconductor substrate, wherein an inner perimeter of the inner isolation structure demarcates a device region;
- an inner ring-shaped well disposed in the semiconductor substrate and laterally surrounding the inner isolation structure;
- an outer isolation structure disposed in the semiconductor substrate and laterally surrounding both the inner ring-shaped well and the inner isolation structure;
- and
- a plurality of dishing prevention dummy gates arranged over both the inner ring-shaped well and the outer isolation structure, wherein a first dishing prevention dummy gate of the plurality of dishing prevention dummy gates comprises a dummy gate dielectric disposed over the inner ring-shaped well, and wherein sidewalls of the dummy gate dielectric are disposed between an inner perimeter of the inner ring-shaped well and an outer perimeter of the inner ring-shaped well.
An integrated circuit (IC), comprising:
- a first ring-shaped isolation structure disposed in a semiconductor substrate, wherein the first ring-shaped isolation structure demarcates a first device region;
- a second ring-shaped isolation structure disposed in the semiconductor substrate and laterally spaced from the first ring-shaped isolation structure, wherein the second ring-shaped isolation structure demarcates a second device region;
- an outer ring-shaped well disposed in the semiconductor substrate and laterally surrounding the first ring-shaped isolation structure;
- a first dishing prevention dummy gate disposed over both the first ring-shaped isolation structure and the second ring-shaped isolation structure, wherein the first dishing prevention dummy gate comprises a first dummy gate dielectric having a first height;
- and
- a second dishing prevention dummy gate disposed over both the first ring-shaped isolation structure and the second ring-shaped isolation structure, wherein the second dishing prevention dummy gate comprises a second dummy gate dielectric having a second height that is greater than the first height.
Dependencies are inferred from the claim text.