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US 10,950,704 B2Granted
Vertical memory devices
AssigneeSamsung Electronics Co., Ltd.
InventorsSeung-Jun Shin, Si-Wan Kim, Bong-Hyun Choi
Life of this patent
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Abstract
A vertical memory device includes a substrate including a cell array region and a staircase region surrounding the cell array region, gate electrodes on the cell array region and the staircase region, and a channel on the cell array region. The gate electrodes are isolated from each other in first and third directions and each extend in a second direction. The channel extends in the first direction through one or more gate electrodes. End portions in the second direction of first gate electrodes of the plurality of gate electrodes define first steps in the second direction and second steps in the third direction on the staircase region of the substrate, the second steps being connected to the first steps, respectively, at same levels.
Claims20
A vertical memory device, comprising:
- a substrate including a cell array region and a staircase region surrounding the cell array region;
- a plurality of gate electrodes on the cell array region and the staircase region of the substrate, the plurality of gate electrodes isolated from direct contact with each other in a first direction, each gate electrode of the plurality of gate electrodes extending in a second direction, the plurality of gate electrodes further isolated from direct contact with each other in a third direction, the first direction being substantially perpendicular to an upper surface of the substrate, the third direction being substantially parallel to the upper surface of the substrate, and the second direction being substantially parallel to the upper surface of the substrate and substantially perpendicular to the third direction;
- and
- a channel on the cell array region of the substrate, the channel extending in the first direction through one or more gate electrodes of the plurality of gate electrodes,
- wherein end portions in the second direction of first gate electrodes of the plurality of gate electrodes define sequential first steps in the second direction and sequential second steps in the third direction on the staircase region of the substrate, the sequential second steps being connected to respective, same-level sequential first steps, to define a plurality of sequential steps each having an “L” shape in a plan view.
2 more elements
A vertical memory device, comprising:
- a substrate including a cell array region and a staircase region surrounding the cell array region;
- a plurality of gate electrodes on the cell array region and the staircase region of the substrate, the plurality of gate electrodes isolated from direct contact with each other in a first direction, each gate electrode of the plurality of gate electrodes extending in a second direction, the plurality of gate electrodes further isolated from direct contact with each other in a third direction, the first direction being substantially perpendicular to an upper surface of the substrate, the third direction being substantially parallel to the upper surface of the substrate, and the second direction being substantially parallel to the upper surface of the substrate and substantially perpendicular to the third direction;
- and
- a channel on the cell array region of the substrate, the channel extending in the first direction through one or more gate electrodes of the plurality of gate electrodes,
- wherein end portions in the second direction of first gate electrodes of the gate electrodes define a plurality of sequential first steps in the second direction on the staircase region of the substrate, the plurality of sequential first steps each having an “L” shape in a plan view,
- wherein end portions in the second direction of second gate electrodes higher than the first gate electrodes among the plurality of gate electrodes define second steps in the second direction and/or the third direction on the staircase region of the substrate, and
- wherein the plurality of sequential first steps are overlapped with the second steps in the first direction.
4 more elements
A vertical memory device, comprising:
- a substrate including a cell array region and a staircase region surrounding the cell array region;
- a plurality of gate electrodes on the cell array region and the staircase region of the substrate, the plurality of gate electrodes isolated from direct contact with each other in a first direction, each gate electrode of the plurality of gate electrodes extending in a second direction, the plurality of gate electrodes further isolated from direct contact with each other in a third direction, the first direction being substantially perpendicular to an upper surface of the substrate, the third direction being substantially parallel to the upper surface of the substrate, and the second direction being substantially parallel to the upper surface of the substrate and substantially perpendicular to the third direction;
- and
- a channel on the cell array region of the substrate, the channel extending in the first direction through one or more gate electrodes of the plurality of gate electrodes,
- wherein end portions in the second direction of first gate electrodes of the plurality of gate electrodes define a plurality of sequential first steps each having an “L” shape in a plan view.
2 more elements
Dependencies are inferred from the claim text.