Silicon carbide planar MOSFET with wave-shaped channel regions

A metal-oxide semiconductor transistor (MOSFET) comprising:

• a silicon carbide (SiC) substrate having top and bottom planar surfaces;
• a drain region of a first conductivity type disposed at the bottom planar surface;
• an extended drain region of a first conductivity type disposed above the drain region;
• a plurality of well regions of a second conductivity type disposed above the extended drain region;
• a plurality of junction field-effect transistor (JFET) regions each of which laterally separates an adjacent pair of well regions, the JFET regions extending up to the top planar surface;
• a plurality of source regions of the first conductivity type correspondingly disposed in the plurality of well regions, each of the source regions extending up to the top planar surface, a channel region of each of the plurality of well regions laterally adjoining one of the plurality of the JFET regions, the channel region extending up to the top planar surface and laterally separating each source region from an adjacent JFET region by a channel length;
• a plurality of body regions of the second conductivity type each of which adjoin a source region, each body region extending up to the top planar surface;
• one or more gate members disposed above the top planar surface, the gate member being insulated from the top planar surface by a thin dielectric layer, the one or more gate members extending laterally over each JFET region and each channel region;
• a top metal layer that electrically contacts the source regions, and a bottom metal layer that electrically contacts the drain region;
• when the MOSFET is in an on-state with a high voltage applied to the one or more gate members relative to the source, a conduction channel is formed below the top planar surface in each channel region such that a current flows laterally from the source regions to the JFET regions, and then in a vertical direction down through the extended drain region to the drain region;
• wherein the JFET regions are each arranged in a serpentine-shaped pattern at the top planar surface, the serpentine-shaped pattern extending in first and second lateral directions, the serpentine pattern including straight sections that extend in a first lateral direction, the straight sections being connected by curved sections that alternately shift the straight sections a predetermined distance in the second lateral direction.