Semiconductor device including a chip capacitor mounted on a wiring substrate

A semiconductor device comprising:

• a wiring substrate;
• a semiconductor chip mounted on the wiring substrate;
• a first chip capacitor mounted on the wiring substrate, the first chip capacitor having a first electrode and a second electrode opposite the first electrode;
• and
• a second chip capacitor mounted on the wiring substrate, the second chip capacitor including a third electrode and a fourth electrode opposite the third electrode,
• wherein the wiring substrate includes:
• a first conductive layer which includes a first terminal pattern, a second terminal pattern, a third terminal pattern, and a fourth terminal pattern;
• and
• an insulating layer which covers the first conductive layer, wherein the insulating layer includes:
• a first opening portion exposing a part of the first terminal pattern;
• a second opening portion exposing a part of the second terminal pattern;
• a third opening portion exposing a part of the third terminal patter;
• and
• a fourth opening portion exposing a part of the fourth terminal pattern,
• wherein, in plan view, the first opening portion and the second opening portion are separated apart from each other such that the insulating layer is located between the first opening portion and the second opening portions,
• wherein, in the plan view, the third opening portion and the fourth opening portion are separated apart from each other such that, the insulating layer is located between the third opening portion and the fourth opening portion,
• wherein the second terminal pattern is not exposed in each of the first opening portion, the third opening portion and the fourth opening portion,
• wherein the first terminal pattern is not exposed in each of the second opening portion, the third opening portion, and the fourth opening portion,
• wherein the fourth terminal pattern is not exposed in each of the first opening portion, the second opening portion, and the third opening portion,
• wherein the third terminal pattern is not exposed in each of the first opening portion, the second opening portion, and the fourth opening portion,
• wherein the first terminal pattern has a first side which faces the second terminal pattern in the plan view,
• wherein the first side of the first terminal pattern is exposed in the first opening portion,
• wherein other sides of the first terminal pattern except the first side is not exposed in the first opening portion,
• wherein the second terminal pattern has a second side which faces the first side of the first terminal pattern in the plan view,
• wherein the second side of the second terminal pattern is exposed in the second opening portion,
• wherein other sides of the second terminal pattern except the second side is not exposed in the second opening portion,
• wherein the third opening portion is disposed inside the third terminal pattern in the plan view,
• wherein the fourth opening portion is disposed inside the fourth terminal pattern in the plan view,
• wherein the first electrode of the first chip capacitor is electrically connected with the first terminal pattern exposed in the first opening portion via a first solder,
• wherein the second electrode of the first chip capacitor is electrically connected with the second terminal pattern exposed in the second opening portion via a second solder,
• wherein the third electrode of the second chip capacitor is electrically connected with the third terminal pattern exposed in the third opening portion via a third solder connected portion, and
• wherein the fourth electrode of the second chip capacitor is electrically connected with the fourth terminal pattern exposed in the fourth opening portion via a fourth solder connected portion.