Array substrate, manufacturing method thereof, and display panel

A method for manufacturing an array substrate, comprising:

• a step S1:
• forming a flexible substrate;
• a step S2:
• depositing an active layer on the flexible substrate and crystalizing the active layer;
• a step S3:
• depositing a first gate insulating layer on the flexible substrate and the active layer;
• a step S4:
• depositing a first gate layer on the first gate insulating layer, image-etching the first gate layer to form a first gate electrode, wherein the first gate layer is a multi-layered metal layer;
• a step S5:
• depositing a second gate insulating layer on the first gate insulating layer and the first gate layer;
• and
• a step S6:
• depositing a second gate layer on the second gate insulating layer and image-etching the second gate layer to from a second gate electrode;
• wherein the second gate layer is a multi-layered metal layer;
• wherein the active layer comprises a source area and a drain area, wherein the method further comprises the following steps between the step S3 and step S4;
• a step S100:
• performing a p-type heavy-doping to the source area and the drain area of the active layer;
• and
• a step S200:
• activating a p-type heavy-doped source area and a p-type heavy-doped drain area, wherein an activating temperature is 450° C. and an activating duration ranges between 30 minutes and 60 minutes.

A method for manufacturing an array substrate, comprising:

• a step S1:
• forming a flexible substrate;
• a step S2:
• depositing an active layer on the flexible substrate and crystalizing the active layer;
• a step S3:
• depositing a first gate insulating layer on the flexible substrate and the active layer;
• a step S4:
• depositing a first gate layer on the first gate insulating layer, image-etching the first gate layer to form a first gate electrode, wherein the first gate layer is a multi-layered metal layer;
• a step S5:
• depositing a second gate insulating layer on the first gate insulating layer and the first gate layer;
• and
• a step S6:
• depositing a second gate layer on the second gate insulating layer and image-etching the second gate layer to from a second gate electrode;
• wherein the second gate layer is a multi-layered metal layer;
• wherein the multi-layered metal layer comprises:
• a first metal layer;
• a second metal layer;
• and
• a third metal layer disposed between the first metal layer and the second metal layer;
• wherein the first metal layer and the second metal layer are composed of titanium or molybdenum, the third metal layer is composed of aluminum.