Array substrate, display panel and display device

An array substrate, comprising:

• a base substrate comprising a plurality of pixel regions arranged in an array;
• a plurality of thin film transistors corresponding to respective ones of the plurality of pixel regions, each of the thin film transistors comprising:
• an active layer on the substrate;
• a gate electrode on the base substrate, wherein the active layer and the gate electrode are stacked on top of each other;
• a source electrode above the gate electrode, wherein the source electrode is electrically connected to the active layer through a first via;
• and
• a drain electrode above the gate electrode, wherein the drain electrode is electrically connected to the active layer through a second via, and wherein the drain electrode comprises a first portion in the second via and a second portion outside the second via;
• a passivation layer on the source electrode and the drain electrode of each of the thin film transistors, wherein the passivation layer is on the first portion of the drain electrode of each of the thin film transistors;
• a plurality of pixel electrodes associated with respective ones of the plurality of pixel regions;
• and
• a planarizing layer on the passivation layer,
• wherein the plurality of pixel electrodes are on the passivation layer,
• wherein each of the pixel electrodes are electrically connected to the drain electrode of a respective one of the thin film transistors through a respective third via of a respective one of the thin film transistors that extends through the passivation layer,
• wherein a respective one of the plurality of pixel electrodes is electrically connected to the second portion of the drain electrode through the respective third via of the respective one of the thin film transistors,
• wherein the planarizing layer is associated with a plurality of fourth vias,
• wherein an orthographic projection of each of the plurality of fourth vias onto the base substrate completely covers an orthographic projection of the respective third via of the respective one of the thin film transistors onto the base substrate, and
• wherein each of the pixel electrodes comprises a third portion in the respective third via, a fourth portion in a respective one of the plurality of fourth vias, and a fifth portion on the planarizing layer.