Circuit and method to enhance efficiency of memory

A semiconductor device, comprising:

• a memory array;
• and
• a modulation circuit configured to generate a first voltage corresponding to a first positive temperature coefficient during a read operation of the memory array, and generate a second voltage corresponding to a first negative temperature coefficient during a write operation of the memory array, the modulation circuit comprising:
• a first node to receive a first current;
• a first resistive element including a first end and a second end, the first end connected to the first node and receiving a first branch current of the first current, the first branch current corresponding to a second positive temperature coefficient;
• first transistors each including a first terminal connected to the second end of the first resistive element;
• and
• a second resistive element connected to the first node and receiving a second branch current of the first current, the second branch current corresponding to a second negative temperature coefficient, wherein the second resistive element being an adjustable resistive element, the second resistive element is adjusted for generating the first voltage corresponding to the first positive temperature coefficient during the read operation, and for generating the second voltage the first negative temperature coefficient during the write operation.

A circuit, comprising:

• a first portion for generating a first current, the first current comprising a first branch current and a second branch current, the first branch current having a first magnitude, the second branch current having a second magnitude, the first portion comprising a first node, a first resistive element, first transistors and a second resistive element, the first node receiving the first current, the first resistive element receiving the first branch current, the second resistive element receiving the second branch current, the second resistive element being an adjustable resistive element;
• a second portion for generating a second current, the second current having the same magnitude as the first current, the second current comprising a first branch current and a second branch current, the first branch current having the first magnitude, the second branch current having the second magnitude, the second portion comprising a second node, a second transistor and a third resistive element, the second node receiving the second current, the second transistor receiving the first branch current of the second current, the third resistive element receiving the second branch current of the second current the third resistive element being an adjustable resistive element;
• and
• an output stage for generating a third current and an output voltage, the third current having the same magnitude as the first current, the output voltage having a first voltage and a second voltage, the first voltage corresponding to a positive temperature coefficient and corresponding to the first magnitude, the second voltage corresponding to a negative temperature coefficient and corresponding to the second magnitude, the output stage comprising a third node and a fourth resistive element, the third node receiving the third current, the fourth resistive element connecting to the third node, the output voltage at the third node the fourth resistive element being an adjustable resistive element.