Semiconductor memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsYoung-Jin Jung, Sunghan Cho
Life of this patent
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Abstract
A semiconductor memory device includes a substrate including a cell array region and a pad region, a stack structure disposed on the cell array region and the pad region of the substrate and including gate electrodes, a device isolation layer vertically overlapping the stack structure and disposed in the pad region of the substrate, a dummy vertical channel portion penetrating the stack structure on the pad region of the substrate and disposed in the device isolation layer, and a dummy semiconductor pillar disposed between the dummy vertical channel portion and one portion of the substrate being in contact with one sidewall of the device isolation layer.
Claims25
A semiconductor memory device comprising:
- a substrate including a cell array region and a pad region;
- a stack structure disposed on the cell array region and the pad region of the substrate and comprising gate electrodes;
- a device isolation layer vertically overlapping the stack structure and disposed in the pad region of the substrate;
- a first dummy vertical channel portion penetrating the stack structure on the pad region of the substrate and disposed in the device isolation layer;
- and
- a first dummy semiconductor pillar disposed between the first dummy vertical channel portion and one portion of the substrate being in contact with one sidewall of the device isolation layer.
A semiconductor memory device comprising:
- a substrate including a cell array region and a pad region;
- a stack structure disposed on the cell array region and the pad region of the substrate and comprising gate electrodes;
- a device isolation layer vertically overlapping the stack structure and disposed in the pad region of the substrate;
- a dummy vertical channel portion penetrating the stack structure on the pad region of the substrate and disposed in the device isolation layer;
- and
- a dummy semiconductor pillar disposed between the dummy vertical channel portion and the substrate in the device isolation layer,
- wherein the dummy vertical channel portion and the dummy semiconductor pillar are spaced apart from each other.
A semiconductor memory device comprising:
- a substrate including a cell array region and a pad region;
- a stack structure disposed on the cell array region and the pad region of the substrate and comprising gate electrodes;
- a device isolation layer vertically overlapping the stack structure and disposed in the pad region of the substrate;
- a dummy vertical channel portion penetrating the stack structure on the pad region of the substrate and disposed in the device isolation layer;
- and
- a dummy semiconductor pillar disposed between the dummy vertical channel portion and the substrate in the device isolation layer,
- wherein a bottom surface of the dummy semiconductor pillar is disposed at a level substantially the same as or higher than that of a bottom surface of the device isolation layer.
Dependencies are inferred from the claim text.