Memory arrays

A memory array, comprising:

• vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:
• a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region, the channel region having a first portion against the first source/drain region and having a second portion along the second source drain region, an insulative material being disposed between the first and second portions;
• and
• a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region;
• horizontally-extending sense-lines in individual of the memory cell tiers, individual of the second source/drain regions in the individual memory cell tiers being electrically coupled to individual of the horizontally-extending sense-lines in the respective individual memory cell tier;
• and
• wordlines electrically coupling together multiple of the gates of individual of the transistors.

A memory array, comprising:

• vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:
• a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region;
• and
• a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region;
• horizontally-extending sense-lines in individual of the memory cell tiers, individual of the second source/drain regions in the individual memory cell tiers being electrically coupled to individual of the horizontally-extending sense-lines in the respective individual memory cell tier, the individual horizontally-extending sense-lines comprising end-to-end-overlapping-interconnected ring-like structures;
• and
• wordlines electrically coupling together multiple of the gates of individual of the transistors.

A memory array, comprising:

• vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:
• a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region;
• and
• a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region;
• wordline structures extending elevationally through the insulative material and the memory cells of the vertically-alternating tiers, individual of the gates that are in different of the memory cell tiers being directly electrically coupled to individual of the wordline structures;
• and
• horizontally-extending sense-lines in individual of the memory cell tiers, individual of the second source/drain regions in the individual memory cell tiers being electrically coupled to individual of the horizontally-extending sense-lines in the respective individual memory cell tier.

A memory array, comprising:

• vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:
• a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region;
• and
• a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region, the second capacitor electrodes of multiple of the capacitors in the array being electrically coupled to one another;
• wordline structures extending elevationally through the insulative material and the memory cells of the vertically-alternating tiers, individual of the gates that are in different of the memory cell tiers being directly electrically coupled to individual of the wordline structures;
• a capacitor-electrode structure extending elevationally through the vertically-alternating tiers, individual of the second electrodes of individual of the capacitors that are in the different memory cell tiers being electrically coupled to the elevationally-extending capacitor-electrode structure;
• and
• sense-lines electrically coupled to multiple of the second source/drain regions of individual of the transistors.

A memory array, comprising:

• vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:
• a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region;
• and
• a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region, the second capacitor electrodes of multiple of the capacitors in the array being electrically coupled to one another;
• horizontally-extending sense-lines in individual of the memory cell tiers, individual of the second source/drain regions in the individual memory cell tiers being electrically coupled to individual of the horizontally-extending sense-lines in the respective individual memory cell tier;
• a capacitor-electrode structure extending elevationally through the vertically-alternating tiers, individual of the second electrodes of individual of the capacitors that are in different of the memory cell tiers being electrically coupled to the elevationally-extending capacitor-electrode structure;
• and
• wordlines electrically coupling together multiple of the gates of individual of the transistors.

A memory array, comprising:

• vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:
• a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region;
• and
• a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region, the second capacitor electrodes of multiple of the capacitors in the array being electrically coupled to one another;
• wordline structures extending elevationally through the insulative material and the memory cells of the vertically-alternating tiers, individual of the gates that are in different of the memory cell tiers being directly electrically coupled to individual of the wordline structures;
• horizontally-extending sense-lines in individual of the memory cell tiers, individual of the second source/drain regions in the individual memory cell tiers being electrically coupled to individual of the horizontally-extending sense-lines in the respective individual memory cell tier;
• and
• a capacitor-electrode structure extending elevationally through the vertically-alternating tiers, individual of the second electrodes of individual of the capacitors that are in the different memory cell tiers being electrically coupled to the elevationally-extending capacitor-electrode structure.