Memory device with multiple layers

A memory device comprising;

• a plurality of word lines, each of the word lines electrically connected to at least one memory cell, the word lines spaced from one another by a first distance in a first direction and extending in a second direction crossing the first direction;
• a first gate layer extending in the second direction, and spaced from one of the word lines nearest thereto by a second distance in the first direction;
• a second gate layer extending in the second direction, and spaced from the plurality of word lines in the first direction, a plurality of memory cells interposed between the second gate layer and the first gate layer;
• a first dummy word line extending in the second direction, and spaced from the plurality of word lines in the first direction by the first distance;
• and
• a second dummy word line extending in the second direction, and spaced from the first dummy word line in the first direction by the first distance, the first and second dummy word lines being between the second gate layer and the plurality of word lines and connected to each other, wherein the second gate layer is spaced from the second dummy word line in the first direction by a third distance that is greater than or equal to 1.5 times the first distance and less than or equal to 3 times the first distance.