Single poly non-volatile memory device, method of manufacturing the same and single poly non-volatile memory device array
AssigneeKey Foundry Co., Ltd.
InventorsSu Jin Kim, Hye Jin Yoo
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Abstract
A single poly non-volatile memory device that includes: a first type lower well; first and second wells separately formed in an upper portion of the first type lower well; a source electrode, a selection transistor, a sensing transistor, and a drain electrode sequentially disposed in an upper portion of the first well. A control gate is formed in an upper portion of the second well with separated on an opposite side of the source electrode from the first well and connected to the gate of the sensing transistor.
Claims20
A method of manufacturing a single poly non-volatile memory device, the method comprising:
- forming a first type lower well by doping first type impurities in a semiconductor substrate;
- forming first and second wells separated in an upper portion of the first type lower well by doping same type impurities;
- forming a first type well to enclose the first and second wells by doping impurities having a conductivity type different than that of the first and second wells;
- and
- forming a selection transistor and a sensing transistor on an upper portion of the first well and simultaneously forming a control gate on an upper portion of the second well separated on an opposite side of a source electrode from the first well.
A method of manufacturing a single poly non-volatile memory device, the method comprising:
- forming a first type lower well by doping first type impurities in a semiconductor substrate formed by doping second type impurities different from the first type impurities;
- forming a first insulating layer in the semiconductor substrate;
- forming first well and second well in the first type lower well by doping same type impurities, wherein the first insulating layer is disposed between the first well and the second well;
- forming a first type well between the first well and the second well by doping impurities having a conductivity type different than that of the first well and the second well;
- forming a selection transistor and a sensing transistor on the first well;
- and
- forming a control gate on the second well,
- wherein the control gate is connected to a gate of the sensing transistor via a floating gate formed on the first insulating layer.
Dependencies are inferred from the claim text.