Three dimensional semiconductor memory with residual memory layer

A semiconductor memory device, comprising:

• a substrate having an uppermost surface;
• a gate stack in which a plurality of gates are vertically stacked on the uppermost surface of the substrate;
• an upper channel extending vertically through the gate stack;
• a lower channel extending from the upper channel to below the uppermost surface of the substrate, the lower channel having a bottom wall and a sidewall projecting upwardly from the bottom wall such that the lower channel has a vertical cross section in a form of an upwardly facing bracket and the sidewall of the lower channel has a top surface and an inner surface;
• a memory layer in the gate stack, surrounding the upper channel, and extending to a level not lower than the uppermost surface of the substrate;
• and
• a residual layer disposed in the substrate, the residual layer being surrounded by the sidewall of the lower channel below the uppermost surface of the substrate,
• wherein the top surface of the sidewall of the lower channel is an uppermost surface of the lower channel and is situated at a level no higher than that of the uppermost surface of the substrate, and
• respective portions of the upper channel and the lower channel constitute a connection structure having an interface along which the upper channel and the lower channel meet such that the upper channel and the lower channel together form a vertical channel, the interface being situated at a level not higher than that of the uppermost surface of the substrate.

A semiconductor memory device, comprising:

• a substrate having a top surface;
• a gate stack including gates disposed one above another on the top surface of the substrate;
• a vertical channel having an upper portion of semiconductor material and a lower portion of semiconductor material;
• a memory layer structure in the gate stack;
• and
• a residual layer disposed below the top surface of the substrate,
• wherein the upper portion of the vertical channel extends vertically through the gate stack,
• the memory layer structure surrounds the upper portion of the vertical channel,
• the lower portion of the vertical channel is disposed in the substrate, the lower portion of the vertical channel having a form of a pot so as to have a bottom wall and a sidewall projecting upwardly from the bottom wall, the sidewall having a top surface in the form of a rim and an inner surface,
• the residual layer is surrounded by the sidewall, and
• the upper portion of the vertical channel and the lower portion of the vertical channel have an interface along which an outer surface of the upper portion of the vertical channel and an inner surface of the lower portion of the vertical channel contact each other and across which a conductive path is established in the device, at least one end of the interface being located no higher than a plane that coincides with the top surface of the substrate.