Asymmetric gate cut isolation for SRAM

An integrated circuit (IC), comprising:

• a static random access memory (SRAM) including:
• a first n-type field effect transistor (NFET) having a first active nanostructure on a substrate, and a first gate surrounding the first active nanostructure;
• a first p-type field effect transistor (PFET) having a second active nanostructure on the substrate adjacent to the first active nanostructure of the first NFET, and a second gate surrounding the second active nanostructure;
• and
• a first gate cut isolation separating the first gate from the second gate, the first gate cut isolation being closer to the second active nanostructure of the first PFET than the first active nanostructure of the first NFET;
• a logic region including:
• a second NFET having a third active nanostructure on the substrate, and a third gate surrounding the third active nanostructure;
• a second PFET having a fourth active nanostructure on the substrate adjacent to the third active nanostructure of the second NFET, and a fourth gate surrounding the fourth active nanostructure;
• and
• a second gate cut isolation equidistant between the third and fourth active nanostructures.