Gate-all-around (GAA) and fin field-effect transistor (FinFet) hybrid static random-access memory (SRAM)

A static random-access memory (SRAM) memory cell comprising:

• a flip-flop (FF) having a pull-up (PU) transistor and a pull-down (PD) transistor;
• and
• a pass-gate (PG) transistor coupled between a bit line (BL) of the SRAM memory cell and the FF, a gate of the PG transistor being coupled to a word line (WL) of the SRAM memory cell, wherein:
• the PG transistor comprises a fin field-effect transistor (FinFET);
• the PD transistor comprises a first gate-all-around (GAA) transistor;
• and
• the PU transistor comprises a second GAA transistor.

A static random-access memory (SRAM), comprising:

• a plurality of memory cells, each of the plurality of memory cells comprising:
• a flip-flop (FF) having a pull-up (PU) transistor and a pull-down (PD) transistor;
• and
• a pass-gate (PG) transistor coupled between a bit line (BL) of the SRAM and the FF, a gate of the PG transistor being coupled to one of a plurality of word lines (WLs) of the SRAM, wherein:
• the PG transistor comprises a first gate-all-around (GAA) transistor;
• the PU transistor comprises a second GAA transistor;
• and
• the PD transistor comprises a fin field-effect transistor (FinFET).