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US 10,950,608 B2Granted
Semiconductor device having junctionless vertical gate transistor and method of manufacturing the same
AssigneesSK hynix Inc., Korea Advanced Institute of Science and Technology
InventorsJung-Min Moon, Tae-Kyun Kim, Seok-Hee Lee
Life of this patent
Estimating the term…
Abstract
A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity.
Claims19
A semiconductor device comprising:
- an active pillar extending upward from a top surface of a substrate;
- a bit line coupled to the active pillar at a first level and buried within the substrate;
- a gate electrode coupled to the active pillar at a second level higher than the first level;
- and
- a capacitor coupled to the active pillar at a third level higher than the second level,
- wherein the first level to the third level of the active pillar are doped with impurities having the same conductivity,
- wherein a top surface of the bit line and a top surface of a liner insulation layer are substantially level with the top surface of the substrate, and
- wherein the bit line is disposed over the liner insulation layer that is disposed along inner sidewalls and a bottom side of a recess within the substrate.
5 more elements
A semiconductor device, comprising:
- an active pillar including a first impurity region, a second impurity region provided over the first impurity region, and a third impurity region provided over the second impurity region and extending upward from a top surface of a substrate;
- a bit line provided below the first impurity region and coupling the first impurity region;
- a gate electrode disposed on a sidewall of the second impurity region;
- and
- a capacitor provided over the third impurity region and coupled to the third impurity region,
- wherein the first, the second, and the third impurity regions of the active pillar contain impurities having the same conductivity,
- wherein a top surface of the bit line and a top surface of a liner insulation layer are substantially level with the top surface of the substrate, and
- wherein the bit line is disposed over the liner insulation layer that is disposed along inner sidewalls and a bottom side of a recess within the substrate.
5 more elements
A semiconductor device, comprising:
- a plurality of active pillars arranged in a first direction, each of the active pillars including a first impurity region disposed over a top surface of a substrate and extending in a second direction crossing the first direction, a plurality of second impurity regions disposed over the first impurity region, and a plurality of third impurity regions disposed over the plurality of second impurity regions, respectively, wherein the plurality of second impurity regions is arranged at a constant interval in the second direction;
- a gate electrode extending across the plurality of active pillars along the first direction and disposed over sidewalls of corresponding second impurity regions of the plurality of active pillars arranged in the first direction;
- and
- a bit line disposed in the substrate under the first impurity region and being in contact with the first impurity region, the bit line extending in the second direction,
- wherein the first, second, and third impurity regions of the active pillar contain impurities of the same conductivity,
- wherein a top surface of the bit line and a top surface of the liner insulation layer are substantially level with the top surface of the substrate, and
- wherein the bit line is disposed over the liner insulation layer that is disposed along inner sidewalls and a bottom side of a recess within the substrate.
4 more elements
Dependencies are inferred from the claim text.