Memory cell array and method of manufacturing same

A method of forming a memory cell array having a memory cell, the method comprising:

• generating, by a processor, a layout design of the memory cell array, the layout design having a corner notch, wherein the generating of the layout design comprises:
• placing a first active region layout pattern adjacent to the corner notch and a first side of the memory cell, and
• placing a second active region layout pattern adjacent to a second side of the memory cell opposite from the first side of the memory cell, the second active region layout pattern being separated from the first active region layout pattern in a first direction, the first active region layout pattern and the second active region layout pattern extending in a second direction and being located on a first layout level;
• wherein at least one of the above layout patterns is stored in a non-transitory computer-readable medium, and at least one of the above generating operations is performed by a hardware processor;
• and
• manufacturing the memory cell array based on the layout design.

A memory cell array comprising:

• a first memory cell arranged in a first row in a first direction;
• a word line extending in the first direction, and being coupled to the first memory cell;
• a first bit line extending in a second direction different from the first direction, and being coupled to the first memory cell;
• wherein the first memory cell corresponds to a five transistor (5T) memory cell, and the first memory cell comprises:
• a first active region having a first length in the second direction;
• and
• a second active region having a second length in the second direction and being different from the first length, the first active region and the second active region extending in the second direction, being located on a first level and being separated from each other in the first direction.