Integrated circuit and method of fabricating the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChung-Te Lin, Ting-Wei Chiang, Hui-Zhong Zhuang, Pin-Dai Sue, Li-Chun Tien
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Abstract
A layout includes a plurality of cells and at least one dummy gate electrode continuously extends across the cells. Since the dummy gate electrode is electrically conductive, the dummy gate electrode can be utilized for interconnecting the cells. That is, some signals may travel through the dummy gate electrode rather than through a metal one line or a metal two line. Therefore, an amount of metal one lines and/or metal two lines for interconnecting the cells can be reduced.
Claims20
An integrated circuit comprising:
- a first cell comprising:
- a first active region having a first longitudinal direction;
- and
- a first gate electrode crossing the first active region;
- a second cell comprising:
- a second active region having a second longitudinal direction parallel to the first longitudinal direction;
- and
- a second gate electrode crossing the second active region, wherein the first gate electrode and the second gate electrode are separated from each other;
- and
- a first dummy gate electrode extending continuously from the first cell to the second cell along a first edge of the first active region and along a second edge of the second active region.
An integrated circuit comprising:
- an first n-type active region having a first longitudinal axis along a first direction;
- a first gate electrode over the first n-type active region and extending perpendicularly to the first direction;
- a first p-type active region having a second longitudinal axis extending along the first direction;
- a second gate electrode over the first p-type active region and extending perpendicularly to the first direction, the second gate electrode being spaced apart from the first gate electrode;
- and
- a first dummy gate electrode extending perpendicularly to the first direction, the first dummy gate electrode disposed between the first n-type active region and the first p-type active region, wherein in a top view, the first dummy gate electrode overlaps with a first end of the first n-type active region and a first end of the first p-type active region.
An integrated circuit comprising:
- a PMOS region having a first longitudinal axis along a first direction, the PMOS region comprising a first p-type active region having a second longitudinal axis along the first direction;
- an NMOS region having a third longitudinal axis along the first direction, the NMOS region comprising a first n-type active region having a fourth longitudinal axis along the first direction;
- a first gate electrode extending continuously from the PMOS region to the NMOS region along a second direction perpendicular to the first direction, wherein in a top view, the first gate electrode overlaps with the first p-type active region and is spaced apart from the first n-type active region;
- and
- a second gate electrode extending continuously from the NMOS region to the PMOS region along the second direction, wherein in the top view, the second gate electrode overlaps with the first n-type active region and is spaced apart from the first p-type active region, wherein there is an offset along the first direction between the first gate electrode and the second gate electrode.
Dependencies are inferred from the claim text.