Chip package structure and manufacturing method thereof

A chip package structure, comprising:

• a redistribution structure layer, comprising:
• at least one redistribution circuit;
• at least one transistor electrically connected to the at least one redistribution circuit;
• a plurality of conductive vias electrically connected to the at least one redistribution circuit and the at least one transistor;
• and
• a plurality of dielectric layers, wherein one of the dielectric layers comprises a first dielectric sub-layer, a second dielectric sub-layer, and a third dielectric sub-layer stacked sequentially, the at least one transistor is located in the dielectric layers, and the at least one transistor comprises:
• a semiconductor material layer located in the second dielectric sub-layer;
• a metal material layer located in the third dielectric sub-layer;
• and
• a conductive material layer penetrating through the third dielectric sub-layer and the second dielectric sub-layer to connect the semiconductor material layer, and the conductive material layer surrounding the metal material layer;
• at least one chip disposed on the redistribution structure layer and electrically connected to the redistribution structure layer;
• and
• an encapsulant disposed on the redistribution structure layer and at least encapsulating the at least one chip.