3D semiconductor device and structure

A 3D semiconductor device, the device comprising:

• a first level,
• wherein said first level comprises a first layer, said first layer comprising first transistors, and
• wherein said first level comprises a second layer, said second layer comprising first interconnections;
• a second level overlaying said first level,
• wherein said second level comprises a third layer, said third layer comprising second transistors, and
• wherein said second level comprises a fourth layer, said fourth layer comprising second interconnections;
• a plurality of connection paths,
• wherein said plurality of connection paths provides connections from a plurality of said first transistors to a plurality of said second transistors,
• wherein said second level is bonded to said first level,
• wherein said bonded comprises oxide to oxide bond regions,
• wherein said bonded comprises metal to metal bond regions,
• wherein said third layer comprises crystalline silicon,
• wherein said second level comprises at least one array of memory cells,
• wherein said memory cells are volatile type memory cells, and
• wherein each of said memory cells are a single transistor memory cell.

A 3D semiconductor device, the device comprising:

• a first level,
• wherein said first level comprises a first layer, said first layer comprising first transistors, and
• wherein said first level comprises a second layer, said second layer comprising first interconnections;
• a second level overlaying said first level,
• wherein said second level comprises a third layer, said third layer comprising second transistors, and
• wherein said second level comprises a fourth layer, said fourth layer comprising second interconnections;
• and
• a plurality of connection paths,
• wherein said plurality of connection paths provides connections from a plurality of said first transistors to a plurality of said second transistors,
• wherein said second level is bonded to said first level,
• wherein said bonded comprises oxide to oxide bond regions,
• wherein said bonded comprises metal to metal bond regions,
• wherein said second level comprises at least one memory array,
• wherein said third layer comprises crystalline silicon, and
• wherein said second layer comprises radio frequency (“RF”) type circuits.