Stacked chip package structure and manufacturing method thereof

A manufacturing method of a stacked chip package structure, comprising:

• disposing a first chip on a carrier, wherein the first chip has a first active surface and a plurality of first pads disposed on the first active surface;
• disposing a second chip on the first chip, wherein the second chip exposes the first pads and has a second active surface and a plurality of second pads disposed on the second active surface;
• forming a plurality of first stud bumps on the first pads;
• forming a plurality of pillar bumps on the second pads;
• encapsulating the first chip and the second chip by an encapsulant, wherein the encapsulant exposes a top surface of each of the pillar bumps;
• forming a plurality of first vias by a laser process, wherein the first vias penetrate the encapsulant and expose the first stud bumps;
• forming a recessed area on each of the first stud bumps by the laser process;
• roughening a surface of the recessed area of each of the first stud bumps by the laser process to form a rough surface;
• forming a conductive layer in the first vias to form a plurality of first conductive vias, wherein after forming the conductive layer in the first vias to form the plurality of first conductive vias, the conductive layer at least partially conforms to the rough surface of each of the first stud bumps;
• and
• removing the carrier, wherein a shape of the plurality of first stud bumps before the step of encapsulating the first chip and the second chip by the encapsulant is substantially the same as a shape of the plurality of first stud bumps after the step of forming the conductive layer in the first vias to form the plurality of first conductive vias, and each of the plurality of first stud bumps includes a protruded knot before the step of encapsulating the first chip and the second chip by the encapsulant.