ILD gap fill for memory device stack array

A semiconductor structure comprising:

• a plurality of electrically conductive structures embedded in an interconnect dielectric material layer and present in a memory device area;
• a memory device stack located on a surface of each electrically conductive structure of the plurality of electrically conductive structures, wherein each memory device stack includes a bottom electrode, a memory device pillar and a top electrode;
• a passivation dielectric material liner located laterally adjacent to each memory device stack and on a surface of the interconnect dielectric material layer;
• and
• a dual interlayer dielectric material structure located on the passivation dielectric material liner and entirely filling a gap between each memory device stack, wherein the dual interlayer dielectric material structure includes, from bottom to top, a first void free low-k interlayer dielectric (ILD) material and a second void free low-k ILD material.