Semiconductor device

A semiconductor device, comprising

• a substrate;
• a first lower wiring line on the substrate;
• a first insulation layer on the first lower wiring line;
• a first dielectric barrier layer on the first insulation layer;
• a first etch stop layer on the first dielectric barrier layer;
• a second insulation layer on the first etch stop layer;
• a first upper wiring film and a first upper wiring barrier film surrounding the first upper wiring film, the first upper wiring film and the first upper wiring barrier film extending through the second insulation layer, the first etch stop layer, the first dielectric barrier layer, and at least part of the first insulation layer;
• a first via barrier film connected to the first upper wiring barrier film and in the first insulation layer, wherein a portion of the first upper wiring barrier film is upwardly curved in a direction away from the substrate,
• wherein the first dielectric barrier layer includes at least one of SiN, SiCN, SiOC, SiON, SiOCN, TiO, TaO, TaTiO, TaSiO and AlO, and the first etch stop layer includes at least one of AlOx, ZrOx, AlN and AlON;
• a third insulation layer on the second insulation layer;
• a second dielectric barrier layer on the third insulation layer;
• a second etch stop layer on the second dielectric barrier layer;
• a fourth insulation layer on the second etch stop layer;
• a second upper wiring barrier film extending through the fourth insulation layer, the second etch stop layer, the second dielectric barrier layer, and the third insulation layer;
• and
• a second via barrier film connected to the first upper wiring barrier film and in the third insulation layer,
• wherein a portion of the second upper wiring barrier film is upwardly curved in a direction away from the substrate.

A semiconductor device comprising:

• a substrate;
• a first lower wiring line on the substrate;
• a first insulation layer on the first lower wiring line;
• a first dielectric barrier layer on the first insulation layer;
• a first etch stop layer on the first dielectric barrier layer;
• a second insulation layer on the first etch stop layer;
• a first upper wiring line extending through the second insulation layer, the first etch stop layer, and the first dielectric barrier layer, and into the first insulation layer;
• and
• a first conductive via in the first insulation layer and electrically connecting the first lower wiring line and the first upper wiring line,
• wherein a portion of an upper surface of the first conductive via protrudes above a portion of a lower surface of the first upper wiring line, and
• wherein the first upper wiring line extends into an upper half of the first insulation layer and does not extend to a lower half of the first insulation layer,
• wherein a distance between a lowest surface of the first upper wiring line and an upper surface of the first insulation layer is a distance between 2 nm and 10 nm.