Redistribution substrate, method of fabricating the same, and semiconductor package including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsJongyoun Kim, Seokhyun Lee, Minjun Bae
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Abstract
A redistribution subtrate, a method of fabricating the same, and a semiconductor package are provided. The method including forming a first conductive pattern; forming a first photosensitive layer on the first conductive pattern, the first photosensitive layer having a first through hole exposing a first portion of the first conductive pattern; forming a first via in the first through hole; removing the first photosensitive layer; forming a first dielectric layer that encapsulates the first conductive pattern and the first via, the first dielectric layer exposing a top surface of the first via; and forming a second conductive pattern on the top surface of the first via.
Claims21
A redistribution substrate comprising:
- a first conductive pattern;
- a first via connected to a first top surface of the first conductive pattern;
- a first dielectric layer that covers the first conductive pattern and surrounds the first via, a first dielectric top surface of the first dielectric layer being coplanar with a first via top surface of the first via;
- a second conductive pattern on the first via, the second conductive pattern including:
- a second conductive pattern pad connected to the first via, and
- a plurality of connection lines spaced apart from the second conductive pattern pad;
- a second via connected to a second top surface of the second conductive pattern pad;
- and
- an under bump pad on the second via,
- wherein a first angle between a first lateral surface of the first via and the first top surface of the first conductive pattern is greater than a second angle between a second lateral surface of the second via and the second top surface of the second conductive pattern pad.
A semiconductor package comprising:
- a first conductive pattern and a second conductive pattern that are vertically spaced apart from each other in a dielectric layer;
- a plurality of first vias that connect the first conductive pattern and the second conductive pattern to each other;
- a plurality of second vias on the second conductive pattern;
- a plurality of under bump pads on the dielectric layer and connected to the plurality of second vias, respectively;
- and
- a semiconductor chip mounted on the plurality of under bump pads,
- wherein each of the plurality of first vias has a pillar shape whose first via width is uniform, and
- wherein each of the plurality of second vias has a tapered shape whose second via width increases with increasing distance from the second conductive pattern,
- wherein the dielectric layer comprises:
- a first dielectric layer that encapsulates the first conductive pattern and the plurality of first vias;
- and
- a second dielectric layer that encapsulates the second conductive pattern and the plurality of second vias, and
- wherein the first dielectric layer has a top surface coplanar with top surfaces of the first vias.
A redistribution substrate comprising:
- a first connection line layer comprising a first pad, and a first via connected to a top surface of the first pad, the first via having a uniform width;
- a second connection line layer comprising a second pad connected to a top surface of the first via, a plurality of connection lines spaced apart from the second pad, and a second via connected to a top surface of the second pad, a second via width of the second via increasing as a distance from the second pad increases;
- and
- an under bump pad on the second via,
- wherein:
- the uniform width is from about 2 μm to about 8 μm;
- a pad width of the second pad is greater than the uniform width;
- and
- a bump pad width of the under bump pad is greater than a maximum width of the second via width.
Dependencies are inferred from the claim text.