Semiconductor device package and method of manufacturing the same

A semiconductor device package, comprising

• a first dielectric layer having a first surface and a second surface opposite to the first surface;
• a conductive pad disposed within the first dielectric layer, the conductive pad comprising:
• a first conductive layer having a first surface exposed from the first dielectric layer and a second surface opposite to the first surface;
• a barrier layer disposed on the second surface of the first conductive layer;
• and
• a second conductive layer disposed on the barrier layer;
• an electrical contact disposed on the first surface of the first conductive layer of the conductive pad and adjacent to the first surface of the first dielectric layer;
• and
• an intermetallic compound (IMC) layer formed between the first conductive layer and the electrical contact, the IMC layer being blocked by the barrier layer without extending into the second conductive layer,
• a seed layer disposed on the second surface of the first dielectric layer;
• a redistribution layer (RDL) disposed on the seed layer;
• and
• a second dielectric layer disposed on the first dielectric layer and partially covering the RDL,
• wherein both the seed layer and the RDL include recess structures,
• wherein an extension line of the first surface of the first dielectric layer passes through the IMC layer.

A semiconductor device package, comprising

• a first dielectric layer having a first surface and a second surface opposite to the first surface;
• a conductive pad disposed within the first dielectric layer, the conductive pad comprising:
• a first conductive layer adjacent to the second surface of the first dielectric layer, the first conductive layer having a first surface facing the first surface of the first dielectric layer and a second surface opposite to the first surface, the second surface of the first conductive layer exposed from the first dielectric layer;
• a barrier layer disposed on the first surface of the first conductive layer;
• and
• a second conductive layer disposed on the barrier layer;
• an electrical contact disposed on the second surface of the first conductive layer of the conductive pad;
• an intermetallic compound (IMC) layer formed between the first conductive layer and the electrical contact;
• a first seed layer disposed on the first surface of the first dielectric layer;
• a first redistribution layer (RDL) disposed on the seed layer;
• a second dielectric layer disposed on the first dielectric layer and partially exposing the first seed layer and the first RDL;
• a second seed layer disposed on the second dielectric layer;
• a second RDL disposed on the second seed layer;
• a third dielectric layer disposed on the second dielectric layer and partially exposing the second seed layer;
• a third seed layer disposed on the third dielectric layer;
• a third RDL disposed on the third seed layer;
• a fourth dielectric layer disposed on the third dielectric layer and partially exposing the third RDL;
• an under bump metallurgy (UBM) layer protruding from the fourth dielectric layer and being electrically connected to the third RDL,
• wherein the first seed layer, the second seed layer, the first RDL, and the second RDL include recess structures, and the recess structure of the first RDL is in contact with the second conductive layer of the conductive pad, and
• wherein a lateral surface of the IMC layer is perpendicular to the second surface of the first dielectric layer.