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US 10,950,528 B2Granted
Chip package assembly and method for manufacturing the same
AssigneeSilergy Semiconductor Technology (Hangzhou) LTD
InventorShijie Chen
Life of this patent
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Abstract
A chip package assembly and a method for manufacturing the same are provided. A die is attached to one of pins located around a chip carrier, so that an electronic component such as a diode is packaged in the chip package assembly and is electrically connected in series with other dies inside the package, thereby improving the degree of integration of the chip package assembly, and reducing a volume of the external circuit.
Claims9
A chip package assembly, comprising:
- a lead frame, having a chip carrier and a plurality of pins located around the chip carrier, wherein the chip carrier has a first surface and a second surface which are opposite to each other, and each of the plurality of pins has a first surface and a second surface which or opposite to each other;
- a first die, mounted on the first surface of the chip carrier;
- and
- one or more second dies, mounted on first surfaces of the plurality of pins, wherein
- each of the second dies comprises a first electrode and a second electrode, the first electrode is electrically connected to a corresponding electrode of the first die, and the second electrode is connected to an external circuit via one of the plurality of pins, so that the second die is connected with the first die in series, or
- each of the second dies comprises a first electrode and a second electrode, the first electrode is electrically connected to a corresponding electrode of the first die, and the second electrode is connected to another corresponding electrode of the first die and is electrically connected to an external circuit via one of the plurality of pins, so that the second die is connected with the first die in parallel.
3 more elements
Dependencies are inferred from the claim text.