Thermal interface material layer and package-on-package device including the same

A semiconductor package device having a package-on-package (PoP) structure, the semiconductor package device comprising:

• a lower semiconductor package including a lower package substrate and a lower semiconductor chip mounted on the lower package substrate, a lower portion of the lower semiconductor chip facing the lower package substrate and being electrically connected to the lower package substrate;
• an upper semiconductor package including an upper package substrate, a first upper semiconductor chip on the upper package substrate and a second upper semiconductor chip, upper portions of the first upper semiconductor chip and the second upper semiconductor chip electrically connected to the upper package substrate through wire bonding, respectively;
• a side interconnection between the upper package substrate and the lower package substrate, the side interconnection electrically connecting the upper semiconductor package and the lower semiconductor package;
• a thermal conductive material disposed between the lower semiconductor package and the upper semiconductor package and spaced apart from an upper surface of the lower semiconductor chip, the thermal conductive material including a resin layer and filler particles distributed in the resin layer;
• and
• a lower mold layer covering both a sidewall of the lower semiconductor chip and surrounding at least a bottom portion of the side interconnection,
• wherein a width of the first upper semiconductor chip in a direction is greater than a width of the lower semiconductor chip in the direction,
• wherein the second upper semiconductor chip exposes an upper surface of the first upper semiconductor chip, and
• wherein the filler particles include at least one of a silicon-based compound and a metal particle.