Integrated circuit package and method

A method comprising:

• forming a through via extending from a dielectric layer, the through via having a convex topmost surface, the through via being formed with a plurality of plating processes, each successive one of the plating processes being performed at a higher plating current density than a previous one of the plating processes;
• placing an integrated circuit die on the dielectric layer adjacent the through via;
• encapsulating the integrated circuit die and the through via with an encapsulant, the encapsulant comprising fillers having an average diameter;
• planarizing the encapsulant such that topmost surfaces of the encapsulant, the integrated circuit die, and the through via are level, wherein after the planarizing, remaining portions of the convex topmost surface of the through via have a first thickness, the first thickness being greater than the average diameter of the fillers;
• and
• forming a redistribution structure on the through via, the encapsulant, and the integrated circuit die, the redistribution structure electrically coupling the through via and the integrated circuit die.

A method comprising:

• forming a first opening in a first dielectric layer, the first opening exposing a first metallization pattern;
• forming a through via comprising:
• depositing a seed layer in the first opening and on portions of the first metallization pattern exposed by the first opening;
• plating a first conductive material layer on the seed layer with a first plating process, the first plating process having a first plating rate;
• plating a second conductive material layer on the first conductive material layer with a second plating process, the second plating process having a second plating rate, the second plating rate being greater than the first plating rate;
• and
• plating a third conductive material layer on the second conductive material layer with a third plating process, the third plating process having a third plating rate, the third plating rate being greater than the second plating rate;
• placing an integrated circuit die on the first dielectric layer adjacent the through via;
• encapsulating the integrated circuit die and the through via with an encapsulant;
• and
• planarizing the encapsulant such that topmost surfaces of the encapsulant, the integrated circuit die, and the through via are level.