Wafer-level fan-out package with enhanced performance

An apparatus comprising:

• a first thinned die comprising a first device layer, a first dielectric layer over the first device layer, and a plurality of first die bumps underneath the first device layer;
• a second die comprising a second device layer, a silicon substrate over the second device layer, and a plurality of second die bumps underneath the second device layer;
• a multilayer redistribution structure formed underneath the first thinned die and the second die;
• a first mold compound residing over the silicon substrate of the second die;
• a second mold compound residing over the multilayer redistribution structure, around and underneath the first thinned die, and around and underneath the second die;
• wherein:
• the second mold compound extends beyond a top surface of the first thinned die to define an opening within the second mold compound and over the first thinned die, such that the top surface of the first thinned die is at a bottom of the opening;
• and
• a top surface of the first mold compound and a top surface of the second mold compound are coplanar;
• a third mold compound filling the opening and in contact with the top surface of the first thinned die, wherein the top surface of the first mold compound, the top surface of the second mold compound, and a top surface of the third mold compound are coplanar;
• and
• a fourth mold compound, which resides over the top surface of the first mold compound, the top surface of the second mold compound, and the top surface of the third mold compound.

A method comprising:

• providing a precursor package that includes a first die, a second die, a first mold compound, and a second mold compound, wherein:
• the first die comprises a first device layer, a first dielectric layer over the first device layer, a first silicon substrate over the first dielectric layer, and a plurality of first die bumps underneath the first device layer;
• the second die comprises a second device layer, a second silicon substrate over the second device layer, and a plurality of second die bumps underneath the second device layer;
• the first mold compound resides over the second silicon substrate of the second die;
• and
• the second mold compound resides around and underneath the first die and the second die;
• such that the second mold compound partially covers sidewalls of the first die, covers a bottom surface of the first die, covers sidewalls and a bottom surface of the second die, partially covers sidewalls of the first mold compound, and encapsulates the first die bumps and the second die bumps, wherein the first mold compound and the first silicon substrate extend vertically beyond a top surface of the second mold compound;
• planarizing a top surface of the precursor package to provide a mold package, such that a top surface of the first mold compound, the top surface of the second mold compound, and a backside of the first silicon substrate are coplanar;
• removing substantially the first silicon substrate to provide a first thinned die and form an opening within the second mold compound and over the first thinned die, wherein the first thinned die has a top surface exposed at a bottom of the opening;
• and
• applying a third mold compound to substantially fill the opening and directly contact the top surface of the first thinned die.