Semiconductor packages including a semiconductor chip and methods of forming the semiconductor packages
AssigneeSK hynix Inc.
InventorsJae Woong Yu, So Hyun Jung
Life of this patent
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Abstract
A package substrate of a semiconductor package includes conductive lines of a first layer disposed on a first surface of a base layer and conductive lines of a second layer disposed on a second surface of the base layer. An opening hole located between a first remaining portion and a second remaining portion to separate the first and second remaining portions from each other. The first remaining portion is electrically connected to a first conductive line among the conductive lines of the second layer, and the second remaining portion is electrically connected to a second conductive line among the conductive lines of the second layer.
Claims10
A semiconductor package comprising:
- a semiconductor chip;
- and
- a package substrate on which the semiconductor chip is mounted,
- wherein the package substrate includes:
- a base layer having a first surface and a second surface which are opposite to each other;
- conductive lines of a first layer disposed on the first surface of the base layer;
- conductive lines of a second layer disposed on the second surface of the base layer and electrically connected to respective ones of the conductive lines of the first layer;
- a plating lead line electrically connected to a first conductive line of the conductive lines of the first layer;
- a first remaining portion electrically coupled to a second conductive line among the conductive lines of the second layer;
- a second remaining portion electrically coupled to a third conductive line among the conductive lines of the second layer;
- an opening hole coupled between the first remaining portion and the second remaining portion to space apart the first remaining portion from the second remaining portion;
- a first plating layer formed on a portion of each of the conductive lines of the first layer;
- and
- a second plating layer formed on a portion of each of the conductive lines of the second layer,
- wherein both the second and third conductive lines are conductive lines and are coupled to substantially the same operation voltages.
A semiconductor package comprising:
- a semiconductor chip;
- and
- a package substrate on which the semiconductor chip is mounted,
- wherein the package substrate includes:
- a base layer having a first surface and a second surface which are opposite to each other;
- a first group of conductive lines and a second group of conductive lines disposed on the first surface of the base layer;
- a third group of conductive lines disposed on the second surface of the base layer and electrically connected to respective ones of the first group of conductive lines;
- a fourth group of conductive lines disposed on the second surface of the base layer and electrically connected to respective ones of the second group of conductive lines;
- a first plating lead line connected to a first conductive line among the first group of conductive lines;
- a second plating lead line connected to a second conductive line among the second group of conductive lines;
- a first opening hole coupled between a first remaining portion and a second remaining portion to space apart the first remaining portion from the second remaining portion and electrically disconnect the third group of conductive lines from each other;
- and
- a second opening hole coupled between a third remaining portion and a fourth remaining portion to space apart the third remaining portion from the fourth remaining portion and electrically disconnect the fourth group of conductive lines from each other,
- wherein both the first and second remaining portions are conductive lines and are coupled to first operation voltages, and
- wherein both the third and fourth remaining portions are another conductive lines and are coupled to second operation voltages different from the first voltages.
Dependencies are inferred from the claim text.