Method of manufacturing a chip package

A method of manufacturing chip package, comprising:

• providing a wafer having a first surface and a second surface opposite thereto, the wafer comprising a plurality of conductive bumps disposed on the first surface;
• forming a first adhesion layer and a first carrier board covering the conductive bumps and the first surface, wherein the first adhesion layer is disposed between the first carrier board and the first surface;
• thinning the wafer from the second surface toward the first surface;
• forming a first insulating layer covering the second surface;
• forming a second adhesion layer and a second carrier board covering the first insulating layer, wherein the second adhesion layer is disposed between the second carrier board and the first insulating layer;
• heating the first adhesion layer to a first temperature, such that the first carrier board and the first adhesion layer are removed;
• forming a plurality of trenches penetrating through the wafer;
• forming a second insulating layer filling the trenches and covering the first surface, and the conductive bumps are exposed from the second insulating layer;
• forming a third adhesion layer and a third carrier board covering the conductive bumps and the second insulating layer filled in the trenches, wherein the third adhesion layer is disposed between the third carrier board and the conductive bumps;
• heating the second adhesion layer to a second temperature, such that the second carrier board and the second adhesion layer are removed;
• heating the third adhesion layer to a third temperature, such that the third carrier board and the third adhesion layer are removed;
• and
• dicing the first insulating layer and the second insulating layer along each trench to form a plurality of chip packages.