Interconnects having air gap spacers

A method, comprising:

• forming a metallization layer on a substrate;
• forming an etch stop layer on the metallization layer;
• forming a dielectric layer on the metallization layer;
• forming a hardmask on the dielectric layer;
• patterning and forming a plurality of vias through the hardmask, the dielectric layer and the etch stop layer and exposing a top surface of the metallization layer;
• forming a polymer-adhering liner layer on sidewalls of the plurality of vias;
• depositing a conductive metal in each of the plurality of vias;
• forming a lithography material on a top surface of the polymer-adhering liner layer and the conductive metal in the plurality of vias and on a top surface of the hardmask disposed between adjacent vias;
• forming one or more first openings by selectively etching exposed portions of the hardmask, the dielectric layer, the etch stop layer and the metallization layer to expose the substrate;
• removing the lithography material and selectively etching the hardmask and the dielectric layer between the adjacent vias to form a second opening exposing the etch stop layer;
• and
• selectively depositing a dielectric polymer in at least a top portion of the one or more first openings and on the polymer-adhering liner layer, wherein the dielectric polymer seals an air gap positioned between a bottom surface of the dielectric polymer and a top surface of the substrate.

A semiconductor structure comprising:

• a substrate;
• a metallization layer disposed on the substrate;
• one or more openings in the metallization layer, the one or more openings configured to expose a top surface of the substrate;
• a polymer-adhering liner layer disposed on the metallization layer;
• and
• a dielectric polymer disposed above a top portion of the one or more openings and on the polymer-adhering liner layer, wherein the dielectric polymer seals an air gap positioned between a bottom surface of the dielectric polymer and the top surface of the substrate.