Integration of finFET device

#This invention relates to the field of integrated circuits. More particularly, this invention relates to fin field effect transistors (finFETs) in integrated circuits.

#An integrated circuit may include finFETs in logic or memory circuits. FinFETs may desirably provide increased on-state currents compared to planar FETs having similar footprints. FinFETs may be formed with the fins having constant pitch and width, and the gates having constant width and pitch, so as to provide a desired circuit density. It may be desirable to have some instances of the finFETs with higher on-state currents than adjacent finFETs, for example in delay circuits or in drivers of static random access memory (SRAM) cells. Forming finFETs with varying on-state currents in constant width and pitch configurations may involve adding additional fins to the finFETs, undesirably increasing footprints of the finFETs. It may further be problematic to increase the on-state current by a fractional amount, such as 50 percent, by adding a fin, since fins are added in integral numbers.

#The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to a more detailed description that is presented later.

#FIG. 1 is a cross section of an example integrated circuit containing finFETs.

#FIG. 2A through FIG. 2H are cross sections of the integrated circuit of FIG. 1, depicted in successive stages of fabrication.

#FIG. 3A and FIG. 3B are perspectives of an example integrated circuit containing an SRAM with finFETs formed according the process of FIG. 1 and FIG. 2A through FIG. 2H.

#The present invention is described with reference to the attached figures. The figures are not drawn to scale and they are provided merely to illustrate the invention. Several aspects of the invention are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of the invention. One skilled in the relevant art, however, will readily recognize that the invention can be practiced without one or more of the specific details or with other methods. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the invention. The present invention is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present invention.

#The following application contains related material and is hereby incorporated in its entirety: application Ser. No. 14/500,002 entitled “METHOD OF PRINTING MULTIPLE STRUCTURE WIDTHS USING SPACER DOUBLE PATTERNING” filed concurrently with this application.

#An integrated circuit containing finFETs may be formed so that fins of the finFETs extend above an isolation oxide formed over a substrate of the integrated circuit. A first finFET has a first exposed fin height and a second finFET has a second exposed fin height; the first exposed fin height and the second exposed fin height are different by at least 25 percent. The exposed fin height is a vertical height of a sidewall of the fin above the isolation oxide. Gates are formed over the fins, extending down the sidewalls of the fins, so that finFETs with greater exposed fin heights have greater effective channel widths and hence greater on-state currents compared with similar finFETs with lesser exposed fin heights.