US 10,950,453 B2Granted

Advanced etching technologies for straight, tall and uniform fins across multiple fin pitch structures

AssigneeIntel Corporation

InventorsMuralidhar S. Ambati, Ritesh Jhaveri, Moosung Kim

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Abstract

Embodiments of the invention describe semiconductor devices with high aspect ratio fins and methods for forming such devices. According to an embodiment, the semiconductor device comprises one or more nested fins and one or more isolated fins. According to an embodiment, a patterned hard mask comprising one or more isolated features and one or more nested features is formed with a hard mask etching process. A first substrate etching process forms isolated and nested fins in the substrate by transferring the pattern of the nested and isolated features of the hard mask into the substrate to a first depth. A second etching process is used to etch through the substrate to a second depth. According to embodiments of the invention, the first etching process utilizes an etching chemistry comprising HBr, O2 and CF4, and the second etching process utilizes an etching chemistry comprising Cl2, Ar, and CH4.

Claims20

Dependent claims

A semiconductor structure, comprising:

a substrate;
a nested grouping of fins extending from the substrate through an isolation layer, the nested grouping of fins comprising:
a first fin having a top and laterally opposite sidewalls and having a height to width aspect ratio, and wherein the height to width aspect ratio is greater than 10:1;
a second fin having a top and laterally opposite sidewalls and having the height to width aspect ratio;
a third fin having a top and laterally opposite sidewalls and having the height to width aspect ratio;
and
a fourth fin having a top and laterally opposite sidewalls and having the height to width aspect ratio, wherein the fourth fin is laterally directly adjacent the third fin at a first spacing, wherein the third fin is laterally directly adjacent the second fin at the first spacing, and wherein the second fin is laterally directly adjacent the first fin at the first spacing;
and
an isolated fin extending from the substrate through the isolation layer, the isolated fin having the height to width aspect ratio, and the isolated fin laterally directly adjacent the first fin at a second spacing greater than 1.5 times the first spacing.

6 more elements

A computing device, comprising:

a board;
a processor electrically and physically coupled to the board, wherein the processor comprises:
a substrate;
a nested grouping of fins extending from the substrate through an isolation layer, the nested grouping of fins comprising:
a first fin having a top and laterally opposite sidewalls and having a height to width aspect ratio, and wherein the height to width aspect ratio is greater than 10:1;
a second fin having a top and laterally opposite sidewalls and having the height to width aspect ratio;
a third fin having a top and laterally opposite sidewalls and having the height to width aspect ratio;
and
a fourth fin having a top and laterally opposite sidewalls and having the height to width aspect ratio, wherein the fourth fin is laterally directly adjacent the third fin at a first spacing, wherein the third fin is laterally directly adjacent the second fin at the first spacing, and wherein the second fin is laterally directly adjacent the first fin at the first spacing;
and
an isolated fin extending from the substrate through the isolation layer, the isolated fin having the height to width aspect ratio, and the isolated fin laterally directly adjacent the first fin at a second spacing greater than 1.5 times the first spacing.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/836,432Filed 31 Mar 2020 · continuation
Priority: 27 Dec 2018
Published: US 2020/0227266 A116 Jul 2020
Granted: 16 Mar 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10P 50/242
Of semiconductor materials: of Group IV materials
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 62/113
Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies: isolations within a…
H10D 62/117
Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies: shapes of semiconductor bodies

Family

PCT/US2013/077626Parent of this division · filed 23 Dec 2013
Application16/234,460Parent of this continuation · filed 27 Dec 2018
US 10,204,794 B2Parent of this division · filed 12 Feb 2019
US 2020/0227266 A1Pre-grant publication · published 16 Jul 2020
US 10,643,855 B2Parent of this continuation
Application15/036,351Parent of this division
Application16/234,460Parent of this division
US 2016/0300725 A1Published application
US 2019/0131138 A1Published application
US 10,950,453 B2This patent

From the US filing history. Foreign family members aren’t listed.