Low energy e-beam contact printing lithography
AssigneesKyoka Utsumi Mimura, Shigeru Utsumi, Takashi Utsumi
InventorTakao Utsumi
Life of this patent
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Abstract
A method comprising contact-free positioning a template mask wafer having a template device pattern relative to a predetermined surface area section of a device pattern wafer. The template mask wafer includes a semitransparent layer. The method includes contact-free aligning one or more mask alignment marks of the template mask wafer with one or more alignment marks of the device pattern wafer and contacting the mask wafer on the device pattern wafer. The method includes transferring a template device pattern of the template mask wafer onto the predetermined surface area section of the device pattern wafer using an electron beam while heat conduction is distributed throughout the mask wafer to maintain a low temperature rise in the mask wafer during the transferring. A system is also provided.
Claims36
A method, comprising:
- positioning a template mask wafer having a template device pattern relative to a predetermined surface area section of a device wafer;
- aligning one or more mask alignment marks of the template mask wafer with one or more alignment marks of the device wafer;
- contacting the mask wafer on the device wafer;
- and
- during the contacting, using an electron beam in an electron beam projection process to transfer a template device pattern of the template mask wafer onto the predetermined surface area section of the device wafer;
- wherein the electron beam is transmitted through a semi-transparent layer of the template mask wafer, and the template mask wafer is spaced apart from the device wafer throughout the positioning and aligning.
A method, comprising:
- positioning a template mask wafer having a template device pattern relative to a predetermined surface area section of a semiconductor device wafer (SDW) having a first intermediate layer;
- aligning one or more mask alignment marks of the template mask wafer with one or more alignment marks of the SDW;
- contacting the mask wafer on the SDW;
- and
- using an electron beam in an electron beam projection process to transfer the template device pattern onto the first intermediate layer in the predetermined surface area section;
- wherein the electron beam is transmitted through a semi-transparent layer of the template mask wafer, and the template mask wafer is spaced apart from the SDW throughout the positioning and aligning.
A system comprising:
- a motion platform;
- a processor coupled to the motion platform, the processor configured to:
- control the motion platform to cause positioning of a template mask wafer having a template device pattern relative to a predetermined surface area section of a device wafer,
- control the motion platform to cause aligning of one or more mask alignment marks of the template mask wafer with one or more alignment marks of the device wafer,
- control the motion platform to cause contacting of the mask wafer with the device wafer;
- control an electron beam in an electron beam projection process to facilitate transfer of a template device pattern of the template mask wafer onto the predetermined surface area section of the device wafer concurrent with the contacting;
- and
- the template mask wafer includes a semi-transparent layer through which the electron beam is transmitted during the electron beam projection process;
- wherein the processor is configured to control the motion platform so that the template mask wafer is spaced apart from the device wafer throughout the positioning and aligning.
A method, comprising:
- positioning relative to a predetermined surface area section of a device wafer a template mask wafer having a template device pattern;
- aligning one or more mask alignment marks of the template mask wafer with one or more alignment marks of the device wafer;
- using an electron beam in an electron beam projection process to transfer a template device pattern of the template mask wafer onto the predetermined surface area section of the device wafer;
- and
- controlling a position of the template mask wafer relative to the device wafer so that the template mask wafer contacts the device wafer during the electron beam projection process, whereby a blurring of the electron beam passing through the template mask wafer is negligibly small.
Dependencies are inferred from the claim text.