Methods of reducing gate spacer loss during semiconductor manufacturing

A method, comprising:

• forming a dummy gate structure disposed adjacent to a source/drain (S/D) feature;
• forming a gate spacer on a sidewall of the dummy gate structure, wherein the gate spacer includes silicon at a first concentration and carbon at a second concentration;
• implanting silicon to a top portion of the gate spacer to form a silicon-rich layer;
• implanting carbon to the silicon-rich layer to form a silicon carbon-rich layer, wherein the silicon carbon-rich layer includes carbon at a third concentration greater than the second concentration;
• forming a high-k metal gate structure in place of the dummy gate structure, wherein the forming includes depositing an interlayer dielectric (ILD) layer over the S/D feature;
• forming a trench in the ILD layer and over the S/D feature;
• and
• forming a dielectric layer in the trench, wherein the dielectric layer differs from the ILD layer in composition.