Shift register unit, control method thereof, gate driving device, display device

A shift register unit comprising:

• an input circuit comprising a first terminal electrically connected to an input terminal of the shift register unit and a second terminal electrically connected to a first node, wherein the input circuit is configured to receive an input signal from the input terminal and configured to control an electrical signal of the first node based on the input signal;
• a first output circuit comprising a first terminal electrically connected to the first node, a second terminal configured to receive a first clock signal, and a third terminal electrically connected to a first output terminal of the shift register unit, wherein the first output circuit is configured to output a first output signal at the first output terminal based on the first clock signal responsive to the electrical signal of the first node;
• a first output signal adjustment circuit comprising a first terminal configured to receive a second clock signal, a second terminal electrically connected to the first output terminal, and a third terminal electrically connected to a first reference signal terminal,
• wherein the first output signal adjustment circuit is configured to provide a first reference signal of the first reference signal terminal to the first output terminal responsive to the second clock signal to decrease an amplitude of the first output signal,
• wherein a polarity of the first reference signal is opposite a polarity of the first output signal,
• wherein the first output signal adjustment circuit comprises a first transistor, and wherein a control terminal of the first transistor is configured to receive the second clock signal, a first terminal of the first transistor is electrically connected to the first output terminal, and a second terminal of the first transistor is electrically connected to the first reference signal terminal,
• wherein an amplitude of an effective level of the second clock signal is less than an amplitude of an effective level of the first clock signal, and a duty cycle of the second clock signal is less than a duty cycle of the first clock signal, and
• wherein a plurality of rising edges of the second clock signal are synchronized with rising edges of the first clock signal.