Shift register unit circuit, method of driving the same, gate drive circuit, and display apparatus

A shift register unit circuit, comprising:

• a first node control circuit configured to supply an active potential from a first scan level terminal to a first node in response to an input pulse from an input terminal being active, to supply an inactive potential from a second scan level terminal to the first node in response to a reset pulse from a reset terminal being active, and to supply an inactive potential from a first reference level terminal to the first node in response to a second node being at an active potential;
• a second node control circuit configured to supply an inactive potential from the first reference level terminal to the second node in response to the first node being at an active potential, and to set the second node at an active potential in response to the first node being at an inactive potential and a reset hold signal from a reset hold terminal being active, wherein the reset hold terminal and the second node tare in conduction with each other when the reset hold signal is active, such that the reset hold signal is transferred from the reset hold terminal to the second node to set the second node at an active potential;
• and
• N output circuits each directly connected to a respective internal node, a respective clock terminal and a respective output terminal, the respective internal node being electrically connected to the first node, N being an integer greater than or equal to 2,
• wherein each of the N output circuits is configured to supply a clock signal from the respective clock terminal to the respective output terminal in response to the respective internal node being at an active potential, to supply an inactive potential from the first reference level terminal to the respective output terminal in response to the second node being at an active potential, and to cause a change in the potential of the respective internal node in response to a change in the potential of the respective output terminal,
• wherein the second node control circuit comprises:
• a first transistor having a gate directly connected to the first node, a first electrode directly-connected to the first reference level terminal, and a second electrode directly connected to the second node;
• a second transistor having a gate directly connected to the reset hold terminal, a first electrode directly connected to the reset hold terminal, and a second electrode directly connected to the second node;
• and a first capacitor directly connected between the second node and the first reference level terminal.