Shift register unit, gate driving circuit, display device and driving method

A shift register unit, comprising:

• a signal input terminal configured to receive an input signal;
• a reset input terminal configured to receive a reset signal;
• a carry input terminal configured to receive a carry input signal;
• a clock signal terminal configured to receive a clock signal;
• a signal output terminal configured to output an output signal;
• a carry output terminal configured to output a carry output signal;
• a first voltage terminal configured to receive an inactive voltage;
• a second voltage terminal configured to receive an inactive voltage;
• a first output circuit configured to transfer the clock signal at the clock signal terminal to the signal output terminal as the output signal in response to a first node being at an active potential, wherein the first node is configured to be at the active potential in response to the input signal at the signal input terminal being active and to be at an inactive potential in response to the reset signal at the reset input terminal being active;
• a second output circuit configured to transfer the clock signal at the clock signal terminal to the carry output terminal as the carry output signal in response to the first node being at the active potential;
• and
• a delay circuit configured to generate a delayed version of the carry input signal in response to the carry input signal at the carry input terminal being active, and to transfer the inactive voltage at the first voltage terminal to the signal output terminal in response to the delayed version of the carry input signal being active.